[GISel][AArch64] Removed unused function declaration and brackets

Author: jyli0116

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -687,7 +687,7 @@ def top16Zero: PatLeaf<(i32 GPR32:$src), [{
          CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 16));
   }]> {
   let GISelLeafPredicateCode = [{
-    return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16))); }];
+    return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 16)); }];
 }
 
 // top32Zero - answer true if the upper 32 bits of $src are 0, false otherwise
@@ -696,7 +696,7 @@ def top32Zero: PatLeaf<(i64 GPR64:$src), [{
          CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 32));
   }]> {
   let GISelLeafPredicateCode = [{ 
-    return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32))); }];
+    return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 32)); }];
 }
 
 // topbitsallzero - Return true if all bits except the lowest bit are known zero
@@ -705,14 +705,14 @@ def topbitsallzero32: PatLeaf<(i32 GPR32:$src), [{
          CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(32, 31));
   }]> {
   let GISelLeafPredicateCode = [{ 
-    return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31))); }];
+    return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(32, 31)); }];
 }
 def topbitsallzero64: PatLeaf<(i64 GPR64:$src), [{
   return Op.getValueType() == MVT::i64 &&
          CurDAG->MaskedValueIsZero(Op, APInt::getHighBitsSet(64, 63));
   }]> {
   let GISelLeafPredicateCode = [{ 
-    return (VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63))); }];
+    return VT && VT->maskedValueIsZero(Reg, APInt::getHighBitsSet(64, 63)); }];
 }
 
 // Node definitions.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -511,16 +511,6 @@ class AArch64InstructionSelector : public InstructionSelector {
   /// Return true if \p MI is a load or store of \p NumBytes bytes.
   bool isLoadStoreOfNumBytes(const MachineInstr &MI, unsigned NumBytes) const;
 
-  /// Return true if top 16 bits of register are zero.
-  bool isTop16Zero(const MachineOperand &MO) const;
-
-  /// Return true if top 32 bits of register are zero.
-  bool isTop32Zero(const MachineOperand &MO) const;
-
-  /// Return true if all bits of register except the lowest bit are known zero.
-  bool isTopBitsAllZero32(const MachineOperand &MO) const;
-  bool isTopBitsAllZero64(const MachineOperand &MO) const;
-
   /// Returns true if \p MI is guaranteed to have the high-half of a 64-bit
   /// register zeroed out. In other words, the result of MI has been explicitly
   /// zero extended.

llvm/utils/TableGen/GlobalISelEmitter.cpp

@@ -1115,9 +1115,8 @@ Error GlobalISelEmitter::importChildMatcher(
     for (const TreePredicateCall &Call : SrcChild.getPredicateCalls()) {
       const TreePredicateFn &Predicate = Call.Fn;
 
-      if (!Predicate.hasGISelLeafPredicateCode()) {
+      if (!Predicate.hasGISelLeafPredicateCode())
         return failedImport("Src pattern child has unsupported predicate");
-      }
       OM.addPredicate<OperandLeafPredicateMatcher>(Predicate);
     }
     return Error::success();