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[CIR][X86] Add support for vpcom builtins
Adds support for the `__builtin_ia32_vpcom` and `__builtin_ia32_vpcomu` builtins. Signed-off-by: vishruth-thimmaiah <[email protected]>
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‎clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp‎

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,62 @@ static mlir::Value emitVecInsert(CIRGenBuilderTy &builder, mlir::Location loc,
168168
return cir::VecInsertOp::create(builder, loc, vec, value, indexVal);
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}
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static mlir::Value emitX86vpcom(CIRGenBuilderTy &builder, mlir::Location loc,
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llvm::SmallVector<mlir::Value> ops,
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bool isSigned) {
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mlir::Value op0 = ops[0];
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mlir::Value op1 = ops[1];
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cir::VectorType ty = cast<cir::VectorType>(op0.getType());
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mlir::Type elementTy = ty.getElementType();
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uint64_t imm =
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ops[2].getDefiningOp<cir::ConstantOp>().getIntValue().getZExtValue() &
182+
0x7;
183+
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cir::CmpOpKind pred;
185+
switch (imm) {
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case 0x0:
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pred = cir::CmpOpKind::lt;
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break;
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case 0x1:
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pred = cir::CmpOpKind::le;
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break;
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case 0x2:
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pred = cir::CmpOpKind::gt;
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break;
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case 0x3:
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pred = cir::CmpOpKind::ge;
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break;
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case 0x4:
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pred = cir::CmpOpKind::eq;
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break;
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case 0x5:
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pred = cir::CmpOpKind::ne;
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break;
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case 0x6:
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return builder.getNullValue(ty, loc); // FALSE
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case 0x7: {
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llvm::APInt allOnes =
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llvm::APInt::getAllOnes(cast<cir::IntType>(elementTy).getWidth());
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return cir::VecSplatOp::create(
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builder, loc, ty,
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builder.getConstAPInt(loc, elementTy, allOnes)); // TRUE
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}
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default:
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llvm_unreachable("Unexpected XOP vpcom/vpcomu predicate");
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}
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if (!isSigned) {
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elementTy = builder.getUIntNTy(cast<cir::IntType>(elementTy).getWidth());
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ty = cir::VectorType::get(elementTy, ty.getSize());
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op0 = builder.createBitcast(op0, ty);
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op1 = builder.createBitcast(op1, ty);
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}
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return builder.createVecCompare(loc, pred, op0, op1);
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}
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mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
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const CallExpr *expr) {
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if (builtinID == Builtin::BI__builtin_cpu_is) {
@@ -900,14 +956,20 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
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case X86::BI__builtin_ia32_ucmpq128_mask:
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case X86::BI__builtin_ia32_ucmpq256_mask:
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case X86::BI__builtin_ia32_ucmpq512_mask:
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cgm.errorNYI(expr->getSourceRange(),
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std::string("unimplemented X86 builtin call: ") +
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getContext().BuiltinInfo.getName(builtinID));
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return {};
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case X86::BI__builtin_ia32_vpcomb:
904964
case X86::BI__builtin_ia32_vpcomw:
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case X86::BI__builtin_ia32_vpcomd:
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case X86::BI__builtin_ia32_vpcomq:
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return emitX86vpcom(builder, getLoc(expr->getExprLoc()), ops, true);
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case X86::BI__builtin_ia32_vpcomub:
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case X86::BI__builtin_ia32_vpcomuw:
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case X86::BI__builtin_ia32_vpcomud:
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case X86::BI__builtin_ia32_vpcomuq:
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return emitX86vpcom(builder, getLoc(expr->getExprLoc()), ops, false);
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case X86::BI__builtin_ia32_kortestcqi:
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case X86::BI__builtin_ia32_kortestchi:
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case X86::BI__builtin_ia32_kortestcsi:

‎clang/test/CIR/CodeGenBuiltins/X86/xop-builtins.c‎

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@@ -0,0 +1,217 @@
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// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +xop -fclangir -emit-cir -o %t.cir -Wall -Werror
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// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
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// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +xop -fclangir -emit-llvm -o %t.ll -Wall -Werror
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// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
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// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +xop -fclangir -emit-cir -o %t.cir -Wall -Werror
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// RUN: FileCheck --check-prefix=CIR --input-file=%t.cir %s
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// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +xop -fclangir -emit-llvm -o %t.ll -Wall -Werror
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// RUN: FileCheck --check-prefix=LLVM --input-file=%t.ll %s
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// RUN: %clang_cc1 -x c -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +xop -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=OGCG
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// RUN: %clang_cc1 -x c++ -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-unknown-linux -target-feature +xop -emit-llvm -o - -Wall -Werror | FileCheck %s -check-prefix=OGCG
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// This test mimics clang/test/CodeGen/X86/xop-builtins.c, which eventually
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// CIR shall be able to support fully.
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#include <x86intrin.h>
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__m128i test_mm_com_epu8(__m128i a, __m128i b) {
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// CIR-LABEL: test_mm_com_epu8
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// CIR: %[[A:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
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// CIR: %[[B:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<16 x !s8i> -> !cir.vector<16 x !u8i>
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %[[A]], %[[B]]) : !cir.vector<16 x !u8i>, !cir.vector<16 x !s8i>
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// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epu8
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// LLVM: %[[CMP:.*]] = icmp ult <16 x i8> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <16 x i1> %[[CMP]] to <16 x i8>
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// LLVM: %{{.*}} = bitcast <16 x i8> %[[RES]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epu8
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// OGCG: %[[CMP:.*]] = icmp ult <16 x i8> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <16 x i1> %[[CMP]] to <16 x i8>
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// OGCG: %{{.*}} = bitcast <16 x i8> %[[RES]] to <2 x i64>
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return _mm_com_epu8(a, b, 0);
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}
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__m128i test_mm_com_epu16(__m128i a, __m128i b) {
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// CIR-LABEL: test_mm_com_epu16
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// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
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// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<8 x !s16i> -> !cir.vector<8 x !u16i>
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %[[VAL1]], %[[VAL2]]) : !cir.vector<8 x !u16i>, !cir.vector<8 x !s16i>
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// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<8 x !s16i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epu16
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// LLVM: %[[CMP:.*]] = icmp ult <8 x i16> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <8 x i1> %[[CMP]] to <8 x i16>
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// LLVM: %{{.*}} = bitcast <8 x i16> %[[RES]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epu16
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// OGCG: %[[CMP:.*]] = icmp ult <8 x i16> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <8 x i1> %[[CMP]] to <8 x i16>
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// OGCG: %{{.*}} = bitcast <8 x i16> %[[RES]] to <2 x i64>
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return _mm_com_epu16(a, b, 0);
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}
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__m128i test_mm_com_epu32(__m128i a, __m128i b) {
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// CIR-LABEL: test_mm_com_epu32
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// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s32i> -> !cir.vector<4 x !u32i>
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// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<4 x !s32i> -> !cir.vector<4 x !u32i>
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %[[VAL1]], %[[VAL2]]) : !cir.vector<4 x !u32i>, !cir.vector<4 x !s32i>
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// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<4 x !s32i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epu32
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// LLVM: %[[CMP:.*]] = icmp ult <4 x i32> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>
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// LLVM: %{{.*}} = bitcast <4 x i32> %[[RES]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epu32
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// OGCG: %[[CMP:.*]] = icmp ult <4 x i32> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>
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// OGCG: %{{.*}} = bitcast <4 x i32> %[[RES]] to <2 x i64>
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return _mm_com_epu32(a, b, 0);
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}
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__m128i test_mm_com_epu64(__m128i a, __m128i b) {
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// CIR-LABEL: test_mm_com_epu64
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// CIR: %[[VAL1:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
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// CIR: %[[VAL2:.*]] = cir.cast bitcast %{{.*}} : !cir.vector<2 x !s64i> -> !cir.vector<2 x !u64i>
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %[[VAL1]], %[[VAL2]]) : !cir.vector<2 x !u64i>, !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epu64
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// LLVM: %[[CMP:.*]] = icmp ult <2 x i64> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epu64
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// OGCG: %[[CMP:.*]] = icmp ult <2 x i64> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
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return _mm_com_epu64(a, b, 0);
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}
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__m128i test_mm_com_epi8(__m128i a, __m128i b) {
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// CIR-LABEL: test_mm_com_epi8
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %{{.*}}, %{{.*}}) : !cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>
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// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<16 x !s8i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epi8
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// LLVM: %[[CMP:.*]] = icmp slt <16 x i8> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <16 x i1> %[[CMP]] to <16 x i8>
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// LLVM: %{{.*}} = bitcast <16 x i8> %[[RES]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epi8
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// OGCG: %[[CMP:.*]] = icmp slt <16 x i8> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <16 x i1> %[[CMP]] to <16 x i8>
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// OGCG: %{{.*}} = bitcast <16 x i8> %[[RES]] to <2 x i64>
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return _mm_com_epi8(a, b, 0);
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}
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__m128i test_mm_com_epi16(__m128i a, __m128i b) {
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// CIR-LABEL: test_mm_com_epi16
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %{{.*}}, %{{.*}}) : !cir.vector<8 x !s16i>, !cir.vector<8 x !s16i>
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// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<8 x !s16i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epi16
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// LLVM: %[[CMP:.*]] = icmp slt <8 x i16> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <8 x i1> %[[CMP]] to <8 x i16>
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// LLVM: %{{.*}} = bitcast <8 x i16> %[[RES]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epi16
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// OGCG: %[[CMP:.*]] = icmp slt <8 x i16> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <8 x i1> %[[CMP]] to <8 x i16>
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// OGCG: %{{.*}} = bitcast <8 x i16> %[[RES]] to <2 x i64>
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return _mm_com_epi16(a, b, 0);
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}
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__m128i test_mm_com_epi32(__m128i a, __m128i b) {
127+
// CIR-LABEL: test_mm_com_epi32
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// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %{{.*}}, %{{.*}}) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>
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// CIR: %[[RES:.*]] = cir.cast bitcast %[[CMP]] : !cir.vector<4 x !s32i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epi32
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// LLVM: %[[CMP:.*]] = icmp slt <4 x i32> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>
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// LLVM: %{{.*}} = bitcast <4 x i32> %[[RES]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epi32
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// OGCG: %[[CMP:.*]] = icmp slt <4 x i32> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <4 x i1> %[[CMP]] to <4 x i32>
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// OGCG: %{{.*}} = bitcast <4 x i32> %[[RES]] to <2 x i64>
140+
return _mm_com_epi32(a, b, 0);
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}
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__m128i test_mm_com_epi64(__m128i a, __m128i b) {
144+
// CIR-LABEL: test_mm_com_epi64
145+
// CIR: %[[CMP:.*]] = cir.vec.cmp(lt, %{{.*}}, %{{.*}}) : !cir.vector<2 x !s64i>, !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epi64
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// LLVM: %[[CMP:.*]] = icmp slt <2 x i64> %{{.*}}, %{{.*}}
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// LLVM: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
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// OGCG-LABEL: test_mm_com_epi64
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// OGCG: %[[CMP:.*]] = icmp slt <2 x i64> %{{.*}}, %{{.*}}
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// OGCG: %[[RES:.*]] = sext <2 x i1> %[[CMP]] to <2 x i64>
154+
return _mm_com_epi64(a, b, 0);
155+
}
156+
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__m128i test_mm_com_epi32_false(__m128i a, __m128i b) {
158+
// CIR-LABEL: test_mm_com_epi32_false
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// CIR: %[[ZERO:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i>
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// CIR: %{{.*}} = cir.cast bitcast %[[ZERO]] : !cir.vector<4 x !s32i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epi32_false
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// LLVM: store <2 x i64> zeroinitializer, ptr %[[A:.*]], align 16
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// LLVM: %[[ZERO:.*]] = load <2 x i64>, ptr %[[A]], align 16
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// LLVM: ret <2 x i64> %[[ZERO]]
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// OGCG-LABEL: test_mm_com_epi32_false
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// OGCG: ret <2 x i64> zeroinitializer
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return _mm_com_epi32(a, b, 6);
170+
}
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__m128i test_mm_com_epu32_false(__m128i a, __m128i b) {
173+
// CIR-LABEL: test_mm_com_epu32_false
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// CIR: %[[ZERO:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i>
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// CIR: %{{.*}} = cir.cast bitcast %[[ZERO]] : !cir.vector<4 x !s32i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epu32_false
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// LLVM: store <2 x i64> zeroinitializer, ptr %[[A:.*]], align 16
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// LLVM: %[[ZERO:.*]] = load <2 x i64>, ptr %[[A]], align 16
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// LLVM: ret <2 x i64> %[[ZERO]]
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// OGCG-LABEL: test_mm_com_epu32_false
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// OGCG: ret <2 x i64> zeroinitializer
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return _mm_com_epu32(a, b, 6);
185+
}
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__m128i test_mm_com_epi32_true(__m128i a, __m128i b) {
188+
// CIR-LABEL: test_mm_com_epi32_true
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// CIR: %[[VAL:.*]] = cir.const #cir.int<-1> : !s32i
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// CIR: %[[SPLAT:.*]] = cir.vec.splat %[[VAL]] : !s32i, !cir.vector<4 x !s32i>
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// CIR: %{{.*}} = cir.cast bitcast %[[SPLAT]] : !cir.vector<4 x !s32i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epi32_true
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// LLVM: store <2 x i64> splat (i64 -1), ptr %[[VAL:.*]], align 16
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// LLVM: %[[SPLAT:.*]] = load <2 x i64>, ptr %[[VAL]], align 16
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// LLVM: ret <2 x i64> %[[SPLAT]]
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// OGCG-LABEL: test_mm_com_epi32_true
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// OGCG: ret <2 x i64> splat (i64 -1)
200+
return _mm_com_epi32(a, b, 7);
201+
}
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__m128i test_mm_com_epu32_true(__m128i a, __m128i b) {
204+
// CIR-LABEL: test_mm_com_epu32_true
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// CIR: %[[VAL:.*]] = cir.const #cir.int<-1> : !s32i
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// CIR: %[[SPLAT:.*]] = cir.vec.splat %[[VAL]] : !s32i, !cir.vector<4 x !s32i>
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// CIR: %{{.*}} = cir.cast bitcast %[[SPLAT]] : !cir.vector<4 x !s32i> -> !cir.vector<2 x !s64i>
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// LLVM-LABEL: test_mm_com_epu32_true
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// LLVM: store <2 x i64> splat (i64 -1), ptr %[[VAL:.*]], align 16
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// LLVM: %[[SPLAT:.*]] = load <2 x i64>, ptr %[[VAL]], align 16
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// LLVM: ret <2 x i64> %[[SPLAT]]
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// OGCG-LABEL: test_mm_com_epu32_true
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// OGCG: ret <2 x i64> splat (i64 -1)
216+
return _mm_com_epu32(a, b, 7);
217+
}

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