@@ -152,12 +152,7 @@ bool SIPostRABundler::run(MachineFunction &MF) {
152152 for (MachineBasicBlock &MBB : MF) {
153153 bool HasIGLPInstrs = llvm::any_of (MBB.instrs (), [](MachineInstr &MI) {
154154 unsigned Opc = MI.getOpcode ();
155- // Bypass a MBB with SCHED_BARRIER as well to make it honored.
156- // If SCHED_BARRIER is embedded between memory operations in a bundle,
157- // that SCHED_BARRIER is not picked up by IGLPmutation in post mi
158- // scheduler phase.
159- return Opc == AMDGPU::SCHED_GROUP_BARRIER || Opc == AMDGPU::IGLP_OPT ||
160- Opc == AMDGPU::SCHED_BARRIER;
155+ return Opc == AMDGPU::SCHED_GROUP_BARRIER || Opc == AMDGPU::IGLP_OPT;
161156 });
162157
163158 // Don't cluster with IGLP instructions.
@@ -190,9 +185,11 @@ bool SIPostRABundler::run(MachineFunction &MF) {
190185 if (I->getNumExplicitDefs () != 0 )
191186 Defs.insert (I->defs ().begin ()->getReg ());
192187 ++ClauseLength;
193- } else if (!I->isMetaInstruction ()) {
194- // Allow meta instructions in between bundle candidates, but do not
195- // start or end a bundle on one.
188+ } else if (!I->isMetaInstruction () ||
189+ I->getOpcode () == AMDGPU::SCHED_BARRIER) {
190+ // SCHED_BARRIER is not bundled to be honored by scheduler later.
191+ // Allow other meta instructions in between bundle candidates, but do
192+ // not start or end a bundle on one.
196193 //
197194 // TODO: It may be better to move meta instructions like dbg_value
198195 // after the bundle. We're relying on the memory legalizer to unbundle
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