Rebase

Created using spr 1.3.6-beta.1

Author: wangpc-pp

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -16215,12 +16215,14 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
   EVT VT = N->getValueType(0);
   EVT OpVT = N0.getValueType();
 
-  // Looking for an equality compare.
   ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
-  if (ISD::isIntEqualitySetCC(Cond))
-    if (SDValue V = combineVectorSizedSetCCEquality(VT, N0, N1, Cond, dl, DAG,
-                                                    Subtarget))
-      return V;
+  // Looking for an equality compare.
+  if (!isIntEqualitySetCC(Cond))
+    return SDValue();
+
+  if (SDValue V =
+          combineVectorSizedSetCCEquality(VT, N0, N1, Cond, dl, DAG, Subtarget))
+    return V;
 
   if (OpVT != MVT::i64 || !Subtarget.is64Bit())
     return SDValue();
@@ -16236,9 +16238,6 @@ static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
       N0.getConstantOperandVal(1) != UINT64_C(0xffffffff))
     return SDValue();
 
-  if (!isIntEqualitySetCC(Cond))
-    return SDValue();
-
   // Don't do this if the sign bit is provably zero, it will be turned back into
   // an AND.
   APInt SignMask = APInt::getOneBitSet(64, 31);

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

@@ -2953,7 +2953,7 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
     Options.AllowedTailExpansions = {3};
   }
 
-  if (IsZeroCmp && ST->hasVInstructions() && ST->enableUnalignedVectorMem()) {
+  if (IsZeroCmp && ST->hasVInstructions()) {
     unsigned VLenB = ST->getRealMinVLen() / 8;
     // The minimum size should be the maximum bytes between `VLen * LMUL_MF8`
     // and `XLen * 2`.