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topperctopperc
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fixup! Really pass the flags to getNode.
1 parent f9f69e7 commit bbc3ce7

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5 files changed

+47
-54
lines changed

5 files changed

+47
-54
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7364,7 +7364,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
73647364
SDNodeFlags Flags;
73657365
Flags.setExact(true);
73667366
Res = DAG.getNode(ISD::SRL, DL, XLenVT, Res,
7367-
DAG.getConstant(3 - Log2, DL, VT));
7367+
DAG.getConstant(3 - Log2, DL, XLenVT), Flags);
73687368
} else if (Log2 > 3) {
73697369
Res = DAG.getNode(ISD::SHL, DL, XLenVT, Res,
73707370
DAG.getConstant(Log2 - 3, DL, XLenVT));

‎llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -78,12 +78,12 @@ define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale
7878
; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:
7979
; CHECK: # %bb.0:
8080
; CHECK-NEXT: csrr a0, vlenb
81-
; CHECK-NEXT: srli a0, a0, 3
82-
; CHECK-NEXT: slli a1, a0, 1
83-
; CHECK-NEXT: add a1, a1, a0
84-
; CHECK-NEXT: add a0, a1, a0
85-
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
86-
; CHECK-NEXT: vslideup.vx v8, v9, a1
81+
; CHECK-NEXT: srli a1, a0, 3
82+
; CHECK-NEXT: srli a0, a0, 2
83+
; CHECK-NEXT: add a0, a0, a1
84+
; CHECK-NEXT: add a1, a0, a1
85+
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
86+
; CHECK-NEXT: vslideup.vx v8, v9, a0
8787
; CHECK-NEXT: ret
8888
%v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
8989
ret <vscale x 4 x i8> %v
@@ -309,12 +309,12 @@ define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vsc
309309
; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:
310310
; CHECK: # %bb.0:
311311
; CHECK-NEXT: csrr a0, vlenb
312-
; CHECK-NEXT: srli a0, a0, 3
313-
; CHECK-NEXT: slli a1, a0, 1
314-
; CHECK-NEXT: add a1, a1, a0
315-
; CHECK-NEXT: add a0, a1, a0
316-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
317-
; CHECK-NEXT: vslideup.vx v8, v10, a1
312+
; CHECK-NEXT: srli a1, a0, 3
313+
; CHECK-NEXT: srli a0, a0, 2
314+
; CHECK-NEXT: add a0, a0, a1
315+
; CHECK-NEXT: add a1, a0, a1
316+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
317+
; CHECK-NEXT: vslideup.vx v8, v10, a0
318318
; CHECK-NEXT: ret
319319
%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
320320
ret <vscale x 16 x i8> %v

‎llvm/test/CodeGen/RISCV/rvv/stepvector.ll‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -637,21 +637,21 @@ define <vscale x 16 x i64> @mul_bigimm_stepvector_nxv16i64() {
637637
; RV32-NEXT: lui a1, 797989
638638
; RV32-NEXT: csrr a2, vlenb
639639
; RV32-NEXT: lui a3, 11557
640-
; RV32-NEXT: lui a4, 92455
641640
; RV32-NEXT: addi a1, a1, -683
642-
; RV32-NEXT: addi a3, a3, -683
641+
; RV32-NEXT: srli a4, a2, 2
643642
; RV32-NEXT: sw a1, 8(sp)
644643
; RV32-NEXT: sw a0, 12(sp)
645-
; RV32-NEXT: srli a0, a2, 3
646-
; RV32-NEXT: addi a1, a4, -1368
647-
; RV32-NEXT: mul a2, a2, a3
648-
; RV32-NEXT: mulhu a1, a0, a1
649-
; RV32-NEXT: slli a3, a0, 1
650-
; RV32-NEXT: slli a0, a0, 6
651-
; RV32-NEXT: sub a0, a0, a3
644+
; RV32-NEXT: slli a0, a2, 3
645+
; RV32-NEXT: sub a0, a0, a4
646+
; RV32-NEXT: lui a1, 92455
647+
; RV32-NEXT: addi a3, a3, -683
648+
; RV32-NEXT: mul a3, a2, a3
649+
; RV32-NEXT: srli a2, a2, 3
650+
; RV32-NEXT: addi a1, a1, -1368
651+
; RV32-NEXT: mulhu a1, a2, a1
652652
; RV32-NEXT: add a0, a1, a0
653653
; RV32-NEXT: addi a1, sp, 8
654-
; RV32-NEXT: sw a2, 0(sp)
654+
; RV32-NEXT: sw a3, 0(sp)
655655
; RV32-NEXT: sw a0, 4(sp)
656656
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
657657
; RV32-NEXT: vlse64.v v8, (a1), zero

‎llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll‎

Lines changed: 15 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2240,20 +2240,19 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
22402240
; CHECK-RV32-LABEL: vand_vx_loop_hoisted_not:
22412241
; CHECK-RV32: # %bb.0: # %entry
22422242
; CHECK-RV32-NEXT: csrr a4, vlenb
2243-
; CHECK-RV32-NEXT: srli a3, a4, 3
2244-
; CHECK-RV32-NEXT: li a2, 64
2243+
; CHECK-RV32-NEXT: srli a2, a4, 3
2244+
; CHECK-RV32-NEXT: li a3, 64
22452245
; CHECK-RV32-NEXT: not a1, a1
2246-
; CHECK-RV32-NEXT: bgeu a2, a3, .LBB98_2
2246+
; CHECK-RV32-NEXT: bgeu a3, a2, .LBB98_2
22472247
; CHECK-RV32-NEXT: # %bb.1:
22482248
; CHECK-RV32-NEXT: li a3, 0
22492249
; CHECK-RV32-NEXT: li a2, 0
22502250
; CHECK-RV32-NEXT: j .LBB98_5
22512251
; CHECK-RV32-NEXT: .LBB98_2: # %vector.ph
22522252
; CHECK-RV32-NEXT: li a2, 0
2253-
; CHECK-RV32-NEXT: slli a3, a3, 2
2254-
; CHECK-RV32-NEXT: neg a3, a3
2255-
; CHECK-RV32-NEXT: andi a3, a3, 256
22562253
; CHECK-RV32-NEXT: srli a4, a4, 1
2254+
; CHECK-RV32-NEXT: neg a3, a4
2255+
; CHECK-RV32-NEXT: andi a3, a3, 256
22572256
; CHECK-RV32-NEXT: li a6, 0
22582257
; CHECK-RV32-NEXT: li a5, 0
22592258
; CHECK-RV32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2334,19 +2333,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23342333
; CHECK-ZVKB-NOZBB32-LABEL: vand_vx_loop_hoisted_not:
23352334
; CHECK-ZVKB-NOZBB32: # %bb.0: # %entry
23362335
; CHECK-ZVKB-NOZBB32-NEXT: csrr a4, vlenb
2337-
; CHECK-ZVKB-NOZBB32-NEXT: srli a3, a4, 3
2338-
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 64
2339-
; CHECK-ZVKB-NOZBB32-NEXT: bgeu a2, a3, .LBB98_2
2336+
; CHECK-ZVKB-NOZBB32-NEXT: srli a2, a4, 3
2337+
; CHECK-ZVKB-NOZBB32-NEXT: li a3, 64
2338+
; CHECK-ZVKB-NOZBB32-NEXT: bgeu a3, a2, .LBB98_2
23402339
; CHECK-ZVKB-NOZBB32-NEXT: # %bb.1:
23412340
; CHECK-ZVKB-NOZBB32-NEXT: li a3, 0
23422341
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 0
23432342
; CHECK-ZVKB-NOZBB32-NEXT: j .LBB98_5
23442343
; CHECK-ZVKB-NOZBB32-NEXT: .LBB98_2: # %vector.ph
23452344
; CHECK-ZVKB-NOZBB32-NEXT: li a2, 0
2346-
; CHECK-ZVKB-NOZBB32-NEXT: slli a3, a3, 2
2347-
; CHECK-ZVKB-NOZBB32-NEXT: neg a3, a3
2348-
; CHECK-ZVKB-NOZBB32-NEXT: andi a3, a3, 256
23492345
; CHECK-ZVKB-NOZBB32-NEXT: srli a4, a4, 1
2346+
; CHECK-ZVKB-NOZBB32-NEXT: neg a3, a4
2347+
; CHECK-ZVKB-NOZBB32-NEXT: andi a3, a3, 256
23502348
; CHECK-ZVKB-NOZBB32-NEXT: li a6, 0
23512349
; CHECK-ZVKB-NOZBB32-NEXT: li a5, 0
23522350
; CHECK-ZVKB-NOZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma
@@ -2429,19 +2427,18 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
24292427
; CHECK-ZVKB-ZBB32-LABEL: vand_vx_loop_hoisted_not:
24302428
; CHECK-ZVKB-ZBB32: # %bb.0: # %entry
24312429
; CHECK-ZVKB-ZBB32-NEXT: csrr a4, vlenb
2432-
; CHECK-ZVKB-ZBB32-NEXT: srli a3, a4, 3
2433-
; CHECK-ZVKB-ZBB32-NEXT: li a2, 64
2434-
; CHECK-ZVKB-ZBB32-NEXT: bgeu a2, a3, .LBB98_2
2430+
; CHECK-ZVKB-ZBB32-NEXT: srli a2, a4, 3
2431+
; CHECK-ZVKB-ZBB32-NEXT: li a3, 64
2432+
; CHECK-ZVKB-ZBB32-NEXT: bgeu a3, a2, .LBB98_2
24352433
; CHECK-ZVKB-ZBB32-NEXT: # %bb.1:
24362434
; CHECK-ZVKB-ZBB32-NEXT: li a3, 0
24372435
; CHECK-ZVKB-ZBB32-NEXT: li a2, 0
24382436
; CHECK-ZVKB-ZBB32-NEXT: j .LBB98_5
24392437
; CHECK-ZVKB-ZBB32-NEXT: .LBB98_2: # %vector.ph
24402438
; CHECK-ZVKB-ZBB32-NEXT: li a2, 0
2441-
; CHECK-ZVKB-ZBB32-NEXT: slli a3, a3, 2
2442-
; CHECK-ZVKB-ZBB32-NEXT: neg a3, a3
2443-
; CHECK-ZVKB-ZBB32-NEXT: andi a3, a3, 256
24442439
; CHECK-ZVKB-ZBB32-NEXT: srli a4, a4, 1
2440+
; CHECK-ZVKB-ZBB32-NEXT: neg a3, a4
2441+
; CHECK-ZVKB-ZBB32-NEXT: andi a3, a3, 256
24452442
; CHECK-ZVKB-ZBB32-NEXT: li a6, 0
24462443
; CHECK-ZVKB-ZBB32-NEXT: li a5, 0
24472444
; CHECK-ZVKB-ZBB32-NEXT: vsetvli a7, zero, e32, m2, ta, ma

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll‎

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -338,16 +338,14 @@ define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>} @v
338338
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma
339339
; CHECK-NEXT: vslideup.vx v10, v9, a1
340340
; CHECK-NEXT: vslideup.vx v8, v12, a1
341-
; CHECK-NEXT: slli a3, a1, 1
341+
; CHECK-NEXT: add a3, a0, a0
342+
; CHECK-NEXT: add a1, a4, a1
342343
; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
343344
; CHECK-NEXT: vslideup.vx v10, v11, a2
344345
; CHECK-NEXT: vslideup.vx v8, v13, a2
345-
; CHECK-NEXT: add a2, a0, a0
346-
; CHECK-NEXT: add a3, a3, a1
347-
; CHECK-NEXT: add a1, a3, a1
348346
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
349-
; CHECK-NEXT: vslideup.vx v8, v14, a3
350-
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma
347+
; CHECK-NEXT: vslideup.vx v8, v14, a4
348+
; CHECK-NEXT: vsetvli zero, a3, e8, m1, ta, ma
351349
; CHECK-NEXT: vslideup.vx v8, v10, a0
352350
; CHECK-NEXT: addi a0, sp, 16
353351
; CHECK-NEXT: vs1r.v v8, (a0)
@@ -381,20 +379,18 @@ define {<2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2 x i8>, <2
381379
; CHECK-NEXT: srli a0, a0, 1
382380
; CHECK-NEXT: add a3, a1, a1
383381
; CHECK-NEXT: add a4, a2, a1
384-
; CHECK-NEXT: slli a5, a1, 1
385-
; CHECK-NEXT: add a6, a0, a0
382+
; CHECK-NEXT: add a5, a0, a0
386383
; CHECK-NEXT: vsetvli zero, a3, e8, mf2, tu, ma
387384
; CHECK-NEXT: vslideup.vx v10, v9, a1
388-
; CHECK-NEXT: add a5, a5, a1
389385
; CHECK-NEXT: vslideup.vx v8, v13, a1
386+
; CHECK-NEXT: add a1, a4, a1
390387
; CHECK-NEXT: vsetvli zero, a4, e8, mf2, tu, ma
391388
; CHECK-NEXT: vslideup.vx v10, v11, a2
392-
; CHECK-NEXT: add a1, a5, a1
393389
; CHECK-NEXT: vslideup.vx v8, v14, a2
394390
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
395-
; CHECK-NEXT: vslideup.vx v10, v12, a5
396-
; CHECK-NEXT: vslideup.vx v8, v15, a5
397-
; CHECK-NEXT: vsetvli zero, a6, e8, m1, ta, ma
391+
; CHECK-NEXT: vslideup.vx v10, v12, a4
392+
; CHECK-NEXT: vslideup.vx v8, v15, a4
393+
; CHECK-NEXT: vsetvli zero, a5, e8, m1, ta, ma
398394
; CHECK-NEXT: vslideup.vx v8, v10, a0
399395
; CHECK-NEXT: addi a0, sp, 16
400396
; CHECK-NEXT: vs1r.v v8, (a0)

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