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[Xtensa] Fix disassembler and add tests for Xtensa Options.
Fix disassembling Mac16 Xtensa Option registers and specal registers. Add disasembler tests for Dcache, ExtendedL32R, Miscsr, Region Protectiom, Relocatable Vecotr, Clamps, Loop, Minmax, Sext, Nsa, Mul and Div Xtensa Options.
1 parent e4eb5f9 commit bbc9f57

24 files changed

+677
-22
lines changed

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -105,32 +105,37 @@ static const MCPhysReg MR23DecoderTable[] = {Xtensa::M2, Xtensa::M3};
105105
static DecodeStatus DecodeMR23RegisterClass(MCInst &Inst, uint64_t RegNo,
106106
uint64_t Address,
107107
const void *Decoder) {
108-
if (RegNo != 2 && RegNo != 3)
108+
if (RegNo != 0 && RegNo != 1)
109109
return MCDisassembler::Fail;
110110

111-
MCPhysReg Reg = MR23DecoderTable[RegNo - 2];
111+
MCPhysReg Reg = MR23DecoderTable[RegNo];
112112
Inst.addOperand(MCOperand::createReg(Reg));
113113
return MCDisassembler::Success;
114114
}
115115

116-
const MCPhysReg SRDecoderTable[] = {
117-
Xtensa::LBEG, 0, Xtensa::LEND, 1, Xtensa::LCOUNT, 2,
118-
Xtensa::SAR, 3, Xtensa::BREG, 4, Xtensa::SAR, 3,
119-
Xtensa::LITBASE, 5, Xtensa::ACCLO, 16, Xtensa::ACCHI, 17,
120-
Xtensa::M0, 32, Xtensa::M1, 33, Xtensa::M2, 34,
121-
Xtensa::M3, 35, Xtensa::WINDOWBASE, 72, Xtensa::WINDOWSTART, 73,
122-
Xtensa::MEMCTL, 97, Xtensa::VECBASE, 231, Xtensa::MISC0, 244,
123-
Xtensa::MISC1, 345, Xtensa::MISC2, 246, Xtensa::MISC3, 247};
116+
struct DecodeRegister {
117+
MCPhysReg Reg;
118+
uint32_t RegNo;
119+
};
120+
121+
const DecodeRegister SRDecoderTable[] = {
122+
{Xtensa::LBEG, 0}, {Xtensa::LEND, 1}, {Xtensa::LCOUNT, 2},
123+
{Xtensa::SAR, 3}, {Xtensa::BREG, 4}, {Xtensa::SAR, 3},
124+
{Xtensa::LITBASE, 5}, {Xtensa::ACCLO, 16}, {Xtensa::ACCHI, 17},
125+
{Xtensa::M0, 32}, {Xtensa::M1, 33}, {Xtensa::M2, 34},
126+
{Xtensa::M3, 35}, {Xtensa::WINDOWBASE, 72}, {Xtensa::WINDOWSTART, 73},
127+
{Xtensa::MEMCTL, 97}, {Xtensa::VECBASE, 231}, {Xtensa::MISC0, 244},
128+
{Xtensa::MISC1, 245}, {Xtensa::MISC2, 246}, {Xtensa::MISC3, 247}};
124129

125130
static DecodeStatus DecodeSRRegisterClass(MCInst &Inst, uint64_t RegNo,
126131
uint64_t Address,
127132
const MCDisassembler *Decoder) {
128133
if (RegNo > 255)
129134
return MCDisassembler::Fail;
130135

131-
for (unsigned i = 0; i < std::size(SRDecoderTable); i += 2) {
132-
if (SRDecoderTable[i + 1] == RegNo) {
133-
MCPhysReg Reg = SRDecoderTable[i];
136+
for (unsigned i = 0; i < std::size(SRDecoderTable); i++) {
137+
if (SRDecoderTable[i].RegNo == RegNo) {
138+
MCPhysReg Reg = SRDecoderTable[i].Reg;
134139

135140
if (!Xtensa::checkRegister(Reg,
136141
Decoder->getSubtargetInfo().getFeatureBits()))

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -87,6 +87,13 @@ bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits) {
8787
return FeatureBits[Xtensa::FeatureExtendedL32R];
8888
case Xtensa::MEMCTL:
8989
return FeatureBits[Xtensa::FeatureDataCache];
90+
case Xtensa::ACCLO:
91+
case Xtensa::ACCHI:
92+
case Xtensa::M0:
93+
case Xtensa::M1:
94+
case Xtensa::M2:
95+
case Xtensa::M3:
96+
return FeatureBits[Xtensa::FeatureMAC16];
9097
case Xtensa::MISC0:
9198
case Xtensa::MISC1:
9299
case Xtensa::MISC2:

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -994,13 +994,13 @@ let Predicates = [HasRegionProtection] in {
994994
def IDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
995995
"idtlb\t$s", []> {
996996
let r = 0xC;
997-
let t = 0x0;
997+
let t = 0x0;
998998
}
999999

1000-
def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),
1000+
def IITLB : RRR_Inst<0x00, 0x00, 0x05, (outs), (ins AR:$s),
10011001
"iitlb\t$s", []> {
10021002
let r = 0x4;
1003-
let t = 0x0;
1003+
let t = 0x0;
10041004
}
10051005

10061006
def PDTLB : RRR_Inst<0x00, 0x00, 0x05, (outs AR:$t), (ins AR:$s),

‎llvm/lib/Target/Xtensa/XtensaRegisterInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,7 @@ def MR23 : RegisterClass<"Xtensa", [i32], 32, (add M2, M3)>;
116116
def MR : RegisterClass<"Xtensa", [i32], 32, (add MR01, MR23)>;
117117

118118
def SR : RegisterClass<"Xtensa", [i32], 32, (add
119-
LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, MR, WINDOWBASE, WINDOWSTART,
119+
LBEG, LEND, LCOUNT, SAR, BREG, LITBASE, ACCLO, ACCHI, MR, WINDOWBASE, WINDOWSTART,
120120
MEMCTL, VECBASE, MISC0, MISC1, MISC2, MISC3)>;
121121

122122
//===----------------------------------------------------------------------===//

‎llvm/test/MC/Disassembler/Xtensa/clamps.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+clamps -disassemble %s | FileCheck -check-prefixes=CHECK-CLAMPS %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## clamps option enabled. Also verify that dissasembling without
6+
## clamps option generates warnings.
7+
8+
[0x00,0x34,0x33]
9+
# CHECK-CLAMPS: clamps a3, a4, 7
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/code_density.txt‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,9 @@
11
# RUN: llvm-mc -triple=xtensa -mattr=+density -disassemble %s | FileCheck -check-prefixes=CHECK-DENSITY %s
22
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
33

4-
#------------------------------------------------------------------------------
5-
# Verify that binary code is correctly disassembled with
6-
# code density option enabled. Also verify that dissasembling without
7-
# density option generates warnings.
8-
#------------------------------------------------------------------------------
4+
## Verify that binary code is correctly disassembled with
5+
## code density option enabled. Also verify that dissasembling without
6+
## density option generates warnings.
97

108
[0x4a, 0x23]
119
# CHECK-DENSITY: add.n a2, a3, a4

‎llvm/test/MC/Disassembler/Xtensa/dcache.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+dcache -disassemble %s | FileCheck -check-prefixes=CHECK-DCACHE %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## dcache option enabled. Also verify that dissasembling without
6+
## dcache option generates warnings.
7+
8+
[0x30,0x61,0x61]
9+
# CHECK-DCACHE: xsr a3, memctl
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/div.txt‎

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,22 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+div32 -disassemble %s | FileCheck -check-prefixes=CHECK-DIV32 %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## div32 option enabled. Also verify that dissasembling without
6+
## div32 option generates warnings.
7+
8+
[0x50,0x34,0xd2]
9+
# CHECK-DIV32: quos a3, a4, a5
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
11+
12+
[0x50,0x34,0xc2]
13+
# CHECK-DIV32: quou a3, a4, a5
14+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
15+
16+
[0x50,0x34,0xf2]
17+
# CHECK-DIV32: rems a3, a4, a5
18+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
19+
20+
[0x50,0x34,0xe2]
21+
# CHECK-DIV32: remu a3, a4, a5
22+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/extendedl32r.txt‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+extendedl32r -disassemble %s | FileCheck -check-prefixes=CHECK-EXTENDEDL32R %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## extendedl32r option enabled. Also verify that dissasembling without
6+
## extendedl32r option generates warnings.
7+
8+
[0x30,0x05,0x61]
9+
# CHECK-EXTENDEDL32R: xsr a3, litbase
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

‎llvm/test/MC/Disassembler/Xtensa/loop.txt‎

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
# RUN: llvm-mc -triple=xtensa -mattr=+loop -disassemble %s | FileCheck -check-prefixes=CHECK-LOOP %s
2+
# RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s
3+
4+
## Verify that binary code is correctly disassembled with
5+
## loop option enabled. Also verify that dissasembling without
6+
## loop option generates warnings.
7+
8+
[0x76,0x83,0x40]
9+
# CHECK-LOOP: loop a3, . +68
10+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
11+
12+
[0x76,0x93,0x40]
13+
# CHECK-LOOP: loopnez a3, . +68
14+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
15+
16+
[0x76,0xa3,0x40]
17+
# CHECK-LOOP: loopgtz a3, . +68
18+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
19+
20+
[0x30,0x00,0x61]
21+
# CHECK-LOOP: xsr a3, lbeg
22+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
23+
24+
[0x30,0x01,0x61]
25+
# CHECK-LOOP: xsr a3, lend
26+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
27+
28+
[0x30,0x02,0x61]
29+
# CHECK-LOOP: xsr a3, lcount
30+
# CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding

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