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Revert "[ARM] Change FastISel Address from a struct to a class. NFC"
This reverts commit d47bc6f. I forgot to commit clang-format cleanup before I pushed this.
1 parent 29129be commit bc02802

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+41
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lines changed

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+41
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‎llvm/lib/Target/ARM/ARMFastISel.cpp‎

Lines changed: 41 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -83,55 +83,23 @@ using namespace llvm;
8383
namespace {
8484

8585
// All possible address modes, plus some.
86-
class Address {
87-
public:
88-
using BaseKind = enum {
86+
struct Address {
87+
enum {
8988
RegBase,
9089
FrameIndexBase
91-
};
90+
} BaseType = RegBase;
9291

93-
private:
94-
BaseKind Kind = RegBase;
9592
union {
9693
unsigned Reg;
9794
int FI;
9895
} Base;
9996

10097
int Offset = 0;
10198

102-
public:
10399
// Innocuous defaults for our address.
104100
Address() {
105101
Base.Reg = 0;
106102
}
107-
108-
void setKind(BaseKind K) { Kind = K; }
109-
BaseKind getKind() const { return Kind; }
110-
bool isRegBase() const { return Kind == RegBase; }
111-
bool isFIBase() const { return Kind == FrameIndexBase; }
112-
113-
void setReg(Register Reg) {
114-
assert(isRegBase() && "Invalid base register access!");
115-
Base.Reg = Reg.id();
116-
}
117-
118-
Register getReg() const {
119-
assert(isRegBase() && "Invalid base register access!");
120-
return Base.Reg;
121-
}
122-
123-
void setFI(int FI) {
124-
assert(isFIBase() && "Invalid base frame index access!");
125-
Base.FI = FI;
126-
}
127-
128-
int getFI() const {
129-
assert(isFIBase() && "Invalid base frame index access!");
130-
return Base.FI;
131-
}
132-
133-
void setOffset(int O) { Offset = O; }
134-
int getOffset() { return Offset; }
135103
};
136104

137105
class ARMFastISel final : public FastISel {
@@ -770,7 +738,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
770738
break;
771739
case Instruction::GetElementPtr: {
772740
Address SavedAddr = Addr;
773-
int TmpOffset = Addr.getOffset();
741+
int TmpOffset = Addr.Offset;
774742

775743
// Iterate through the GEP folding the constants into offsets where
776744
// we can.
@@ -806,7 +774,7 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
806774
}
807775

808776
// Try to grab the base operand now.
809-
Addr.setOffset(TmpOffset);
777+
Addr.Offset = TmpOffset;
810778
if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
811779

812780
// We failed, restore everything and try the other options.
@@ -820,17 +788,17 @@ bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
820788
DenseMap<const AllocaInst*, int>::iterator SI =
821789
FuncInfo.StaticAllocaMap.find(AI);
822790
if (SI != FuncInfo.StaticAllocaMap.end()) {
823-
Addr.setKind(Address::FrameIndexBase);
824-
Addr.setFI(SI->second);
791+
Addr.BaseType = Address::FrameIndexBase;
792+
Addr.Base.FI = SI->second;
825793
return true;
826794
}
827795
break;
828796
}
829797
}
830798

831799
// Try to get this in a register if nothing else has worked.
832-
if (!Addr.getReg()) Addr.setReg(getRegForValue(Obj));
833-
return Addr.getReg();
800+
if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
801+
return Addr.Base.Reg != 0;
834802
}
835803

836804
void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
@@ -843,45 +811,45 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
843811
case MVT::i32:
844812
if (!useAM3) {
845813
// Integer loads/stores handle 12-bit offsets.
846-
needsLowering = ((Addr.getOffset() & 0xfff) != Addr.getOffset());
814+
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
847815
// Handle negative offsets.
848816
if (needsLowering && isThumb2)
849-
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.getOffset() < 0 &&
850-
Addr.getOffset() > -256);
817+
needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
818+
Addr.Offset > -256);
851819
} else {
852820
// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
853-
needsLowering = (Addr.getOffset() > 255 || Addr.getOffset() < -255);
821+
needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
854822
}
855823
break;
856824
case MVT::f32:
857825
case MVT::f64:
858826
// Floating point operands handle 8-bit offsets.
859-
needsLowering = ((Addr.getOffset() & 0xff) != Addr.getOffset());
827+
needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
860828
break;
861829
}
862830

863831
// If this is a stack pointer and the offset needs to be simplified then
864832
// put the alloca address into a register, set the base type back to
865833
// register and continue. This should almost never happen.
866-
if (needsLowering && Addr.isFIBase()) {
834+
if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
867835
const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
868836
: &ARM::GPRRegClass;
869837
Register ResultReg = createResultReg(RC);
870838
unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
871839
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
872840
TII.get(Opc), ResultReg)
873-
.addFrameIndex(Addr.getFI())
841+
.addFrameIndex(Addr.Base.FI)
874842
.addImm(0));
875-
Addr.setKind(Address::RegBase);
876-
Addr.setReg(ResultReg);
843+
Addr.Base.Reg = ResultReg;
844+
Addr.BaseType = Address::RegBase;
877845
}
878846

879847
// Since the offset is too large for the load/store instruction
880848
// get the reg+offset into a register.
881849
if (needsLowering) {
882-
Addr.setReg(fastEmit_ri_(MVT::i32, ISD::ADD, Addr.getReg(),
883-
Addr.getOffset(), MVT::i32));
884-
Addr.setOffset(0);
850+
Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
851+
Addr.Offset, MVT::i32);
852+
Addr.Offset = 0;
885853
}
886854
}
887855

@@ -892,12 +860,12 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
892860
// addrmode5 output depends on the selection dag addressing dividing the
893861
// offset by 4 that it then later multiplies. Do this here as well.
894862
if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
895-
Addr.setOffset(Addr.getOffset() / 4);
863+
Addr.Offset /= 4;
896864

897865
// Frame base works a bit differently. Handle it separately.
898-
if (Addr.isFIBase()) {
899-
int FI = Addr.getFI();
900-
int Offset = Addr.getOffset();
866+
if (Addr.BaseType == Address::FrameIndexBase) {
867+
int FI = Addr.Base.FI;
868+
int Offset = Addr.Offset;
901869
MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
902870
MachinePointerInfo::getFixedStack(*FuncInfo.MF, FI, Offset), Flags,
903871
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
@@ -907,25 +875,25 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
907875
// ARM halfword load/stores and signed byte loads need an additional
908876
// operand.
909877
if (useAM3) {
910-
int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset()) : Addr.getOffset();
878+
int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
911879
MIB.addReg(0);
912880
MIB.addImm(Imm);
913881
} else {
914-
MIB.addImm(Addr.getOffset());
882+
MIB.addImm(Addr.Offset);
915883
}
916884
MIB.addMemOperand(MMO);
917885
} else {
918886
// Now add the rest of the operands.
919-
MIB.addReg(Addr.getReg());
887+
MIB.addReg(Addr.Base.Reg);
920888

921889
// ARM halfword load/stores and signed byte loads need an additional
922890
// operand.
923891
if (useAM3) {
924-
int Imm = (Addr.getOffset() < 0) ? (0x100 | -Addr.getOffset()) : Addr.getOffset();
892+
int Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
925893
MIB.addReg(0);
926894
MIB.addImm(Imm);
927895
} else {
928-
MIB.addImm(Addr.getOffset());
896+
MIB.addImm(Addr.Offset);
929897
}
930898
}
931899
AddOptionalDefs(MIB);
@@ -944,7 +912,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
944912
case MVT::i1:
945913
case MVT::i8:
946914
if (isThumb2) {
947-
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
915+
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
948916
Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
949917
else
950918
Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
@@ -964,7 +932,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
964932
return false;
965933

966934
if (isThumb2) {
967-
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
935+
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
968936
Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
969937
else
970938
Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
@@ -980,7 +948,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
980948
return false;
981949

982950
if (isThumb2) {
983-
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
951+
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
984952
Opc = ARM::t2LDRi8;
985953
else
986954
Opc = ARM::t2LDRi12;
@@ -1093,7 +1061,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
10931061
}
10941062
case MVT::i8:
10951063
if (isThumb2) {
1096-
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
1064+
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
10971065
StrOpc = ARM::t2STRBi8;
10981066
else
10991067
StrOpc = ARM::t2STRBi12;
@@ -1107,7 +1075,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
11071075
return false;
11081076

11091077
if (isThumb2) {
1110-
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
1078+
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
11111079
StrOpc = ARM::t2STRHi8;
11121080
else
11131081
StrOpc = ARM::t2STRHi12;
@@ -1122,7 +1090,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, Register SrcReg, Address &Addr,
11221090
return false;
11231091

11241092
if (isThumb2) {
1125-
if (Addr.getOffset() < 0 && Addr.getOffset() > -256 && Subtarget->hasV6T2Ops())
1093+
if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
11261094
StrOpc = ARM::t2STRi8;
11271095
else
11281096
StrOpc = ARM::t2STRi12;
@@ -2063,9 +2031,9 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
20632031
continue;
20642032

20652033
Address Addr;
2066-
Addr.setKind(Address::RegBase);
2067-
Addr.setReg(ARM::SP);
2068-
Addr.setOffset(VA.getLocMemOffset());
2034+
Addr.BaseType = Address::RegBase;
2035+
Addr.Base.Reg = ARM::SP;
2036+
Addr.Offset = VA.getLocMemOffset();
20692037

20702038
bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
20712039
assert(EmitRet && "Could not emit a store for argument!");
@@ -2538,8 +2506,8 @@ bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
25382506

25392507
unsigned Size = VT.getSizeInBits()/8;
25402508
Len -= Size;
2541-
Dest.setOffset(Dest.getOffset() + Size);
2542-
Src.setOffset(Src.getOffset() + Size);
2509+
Dest.Offset += Size;
2510+
Src.Offset += Size;
25432511
}
25442512

25452513
return true;

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