@@ -3237,20 +3237,20 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
32373237 &AArch64::GPR64noipRegClass);
32383238 return BB;
32393239 case AArch64::AUTH_TCRETURN:
3240- fixupBlendComponents (MI, BB, MI.getOperand(3), MI.getOperand(4),
3241- &AArch64::tcGPR64RegClass);
3240+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(3), MI.getOperand(4),
3241+ &AArch64::tcGPR64RegClass);
32423242 return BB;
32433243 case AArch64::AUTH_TCRETURN_BTI:
3244- fixupBlendComponents (MI, BB, MI.getOperand(3), MI.getOperand(4),
3245- &AArch64::tcGPRnotx16x17RegClass);
3244+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(3), MI.getOperand(4),
3245+ &AArch64::tcGPRnotx16x17RegClass);
32463246 return BB;
32473247 case AArch64::BLRA:
3248- fixupBlendComponents (MI, BB, MI.getOperand(2), MI.getOperand(3),
3249- &AArch64::GPR64noipRegClass);
3248+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(2), MI.getOperand(3),
3249+ &AArch64::GPR64noipRegClass);
32503250 return BB;
32513251 case AArch64::BLRA_RVMARKER:
3252- fixupBlendComponents (MI, BB, MI.getOperand(4), MI.getOperand(5),
3253- &AArch64::GPR64noipRegClass);
3252+ fixupPtrauthDiscriminator (MI, BB, MI.getOperand(4), MI.getOperand(5),
3253+ &AArch64::GPR64noipRegClass);
32543254 return BB;
32553255 }
32563256}
0 commit comments