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[X86][APX] Add NF instructions to convertToThreeAddress functions (#130969)
Since #130488, we have NF instructions when converting to three address instructions.
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2 files changed

+117
-37
lines changed

2 files changed

+117
-37
lines changed

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 42 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1283,11 +1283,14 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
12831283

12841284
MachineInstrBuilder MIB =
12851285
BuildMI(MBB, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
1286+
#define CASE_NF(OP) \
1287+
case X86::OP: \
1288+
case X86::OP##_NF:
12861289
switch (MIOpc) {
12871290
default:
12881291
llvm_unreachable("Unreachable!");
1289-
case X86::SHL8ri:
1290-
case X86::SHL16ri: {
1292+
CASE_NF(SHL8ri)
1293+
CASE_NF(SHL16ri) {
12911294
unsigned ShAmt = MI.getOperand(2).getImm();
12921295
MIB.addReg(0)
12931296
.addImm(1LL << ShAmt)
@@ -1296,23 +1299,23 @@ MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
12961299
.addReg(0);
12971300
break;
12981301
}
1299-
case X86::INC8r:
1300-
case X86::INC16r:
1302+
CASE_NF(INC8r)
1303+
CASE_NF(INC16r)
13011304
addRegOffset(MIB, InRegLEA, true, 1);
13021305
break;
1303-
case X86::DEC8r:
1304-
case X86::DEC16r:
1306+
CASE_NF(DEC8r)
1307+
CASE_NF(DEC16r)
13051308
addRegOffset(MIB, InRegLEA, true, -1);
13061309
break;
1307-
case X86::ADD8ri:
1310+
CASE_NF(ADD8ri)
1311+
CASE_NF(ADD16ri)
13081312
case X86::ADD8ri_DB:
1309-
case X86::ADD16ri:
13101313
case X86::ADD16ri_DB:
13111314
addRegOffset(MIB, InRegLEA, true, MI.getOperand(2).getImm());
13121315
break;
1313-
case X86::ADD8rr:
1316+
CASE_NF(ADD8rr)
1317+
CASE_NF(ADD16rr)
13141318
case X86::ADD8rr_DB:
1315-
case X86::ADD16rr:
13161319
case X86::ADD16rr_DB: {
13171320
Src2 = MI.getOperand(2).getReg();
13181321
Src2SubReg = MI.getOperand(2).getSubReg();
@@ -1449,7 +1452,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
14491452
switch (MIOpc) {
14501453
default:
14511454
llvm_unreachable("Unreachable!");
1452-
case X86::SHL64ri: {
1455+
CASE_NF(SHL64ri) {
14531456
assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
14541457
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
14551458
if (!isTruncatedShiftCountForLEA(ShAmt))
@@ -1469,7 +1472,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
14691472
.addReg(0);
14701473
break;
14711474
}
1472-
case X86::SHL32ri: {
1475+
CASE_NF(SHL32ri) {
14731476
assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
14741477
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
14751478
if (!isTruncatedShiftCountForLEA(ShAmt))
@@ -1501,20 +1504,20 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
15011504
LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
15021505
break;
15031506
}
1504-
case X86::SHL8ri:
1507+
CASE_NF(SHL8ri)
15051508
Is8BitOp = true;
15061509
[[fallthrough]];
1507-
case X86::SHL16ri: {
1510+
CASE_NF(SHL16ri) {
15081511
assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
15091512
unsigned ShAmt = getTruncatedShiftCount(MI, 2);
15101513
if (!isTruncatedShiftCountForLEA(ShAmt))
15111514
return nullptr;
15121515
return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
15131516
}
1514-
case X86::INC64r:
1515-
case X86::INC32r: {
1517+
CASE_NF(INC64r)
1518+
CASE_NF(INC32r) {
15161519
assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
1517-
unsigned Opc = MIOpc == X86::INC64r
1520+
unsigned Opc = (MIOpc == X86::INC64r || MIOpc == X86::INC64r_NF)
15181521
? X86::LEA64r
15191522
: (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
15201523
bool isKill;
@@ -1536,10 +1539,10 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
15361539
LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
15371540
break;
15381541
}
1539-
case X86::DEC64r:
1540-
case X86::DEC32r: {
1542+
CASE_NF(DEC64r)
1543+
CASE_NF(DEC32r) {
15411544
assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
1542-
unsigned Opc = MIOpc == X86::DEC64r
1545+
unsigned Opc = (MIOpc == X86::DEC64r || MIOpc == X86::DEC64r_NF)
15431546
? X86::LEA64r
15441547
: (Is64Bit ? X86::LEA64_32r : X86::LEA32r);
15451548

@@ -1562,20 +1565,21 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
15621565
LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
15631566
break;
15641567
}
1565-
case X86::DEC8r:
1566-
case X86::INC8r:
1568+
CASE_NF(DEC8r)
1569+
CASE_NF(INC8r)
15671570
Is8BitOp = true;
15681571
[[fallthrough]];
1569-
case X86::DEC16r:
1570-
case X86::INC16r:
1572+
CASE_NF(DEC16r)
1573+
CASE_NF(INC16r)
15711574
return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1572-
case X86::ADD64rr:
1575+
CASE_NF(ADD64rr)
1576+
CASE_NF(ADD32rr)
15731577
case X86::ADD64rr_DB:
1574-
case X86::ADD32rr:
15751578
case X86::ADD32rr_DB: {
15761579
assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
15771580
unsigned Opc;
1578-
if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
1581+
if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_NF ||
1582+
MIOpc == X86::ADD64rr_DB)
15791583
Opc = X86::LEA64r;
15801584
else
15811585
Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
@@ -1620,21 +1624,21 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
16201624
NumRegOperands = 3;
16211625
break;
16221626
}
1623-
case X86::ADD8rr:
1627+
CASE_NF(ADD8rr)
16241628
case X86::ADD8rr_DB:
16251629
Is8BitOp = true;
16261630
[[fallthrough]];
1627-
case X86::ADD16rr:
1631+
CASE_NF(ADD16rr)
16281632
case X86::ADD16rr_DB:
16291633
return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1630-
case X86::ADD64ri32:
1634+
CASE_NF(ADD64ri32)
16311635
case X86::ADD64ri32_DB:
16321636
assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
16331637
NewMI = addOffset(
16341638
BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src),
16351639
MI.getOperand(2));
16361640
break;
1637-
case X86::ADD32ri:
1641+
CASE_NF(ADD32ri)
16381642
case X86::ADD32ri_DB: {
16391643
assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
16401644
unsigned Opc = Is64Bit ? X86::LEA64_32r : X86::LEA32r;
@@ -1659,18 +1663,18 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
16591663
LV->getVarInfo(SrcReg).Kills.push_back(NewMI);
16601664
break;
16611665
}
1662-
case X86::ADD8ri:
1666+
CASE_NF(ADD8ri)
16631667
case X86::ADD8ri_DB:
16641668
Is8BitOp = true;
16651669
[[fallthrough]];
1666-
case X86::ADD16ri:
1670+
CASE_NF(ADD16ri)
16671671
case X86::ADD16ri_DB:
16681672
return convertToThreeAddressWithLEA(MIOpc, MI, LV, LIS, Is8BitOp);
1669-
case X86::SUB8ri:
1670-
case X86::SUB16ri:
1673+
CASE_NF(SUB8ri)
1674+
CASE_NF(SUB16ri)
16711675
/// FIXME: Support these similar to ADD8ri/ADD16ri*.
16721676
return nullptr;
1673-
case X86::SUB32ri: {
1677+
CASE_NF(SUB32ri) {
16741678
if (!MI.getOperand(2).isImm())
16751679
return nullptr;
16761680
int64_t Imm = MI.getOperand(2).getImm();
@@ -1701,7 +1705,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
17011705
break;
17021706
}
17031707

1704-
case X86::SUB64ri32: {
1708+
CASE_NF(SUB64ri32) {
17051709
if (!MI.getOperand(2).isImm())
17061710
return nullptr;
17071711
int64_t Imm = MI.getOperand(2).getImm();
@@ -2034,6 +2038,7 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr &MI,
20342038
break;
20352039
}
20362040
}
2041+
#undef CASE_NF
20372042

20382043
if (!NewMI)
20392044
return nullptr;

‎llvm/test/CodeGen/X86/apx/nf-regressions.ll‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,75 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc < %s -mtriple=x86_64 -mattr=+nf -verify-machineinstrs | FileCheck %s
3+
4+
define void @convertToThreeAddress(ptr %arg, ptr %arg1) {
5+
; CHECK-LABEL: convertToThreeAddress:
6+
; CHECK: # %bb.0: # %entry
7+
; CHECK-NEXT: movslq (%rdi), %rax
8+
; CHECK-NEXT: movslq (%rsi), %rcx
9+
; CHECK-NEXT: subq %rax, %rcx
10+
; CHECK-NEXT: leaq 1(%rcx), %rax
11+
; CHECK-NEXT: js .LBB0_1
12+
; CHECK-NEXT: .p2align 4
13+
; CHECK-NEXT: .LBB0_6: # %bb
14+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
15+
; CHECK-NEXT: cmpq $1, %rax
16+
; CHECK-NEXT: jg .LBB0_6
17+
; CHECK-NEXT: .LBB0_5: # %bb16
18+
; CHECK-NEXT: retq
19+
; CHECK-NEXT: .LBB0_1:
20+
; CHECK-NEXT: xorl %edx, %edx
21+
; CHECK-NEXT: .p2align 4
22+
; CHECK-NEXT: .LBB0_2: # %bb10
23+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
24+
; CHECK-NEXT: testb %dl, %dl
25+
; CHECK-NEXT: je .LBB0_3
26+
; CHECK-NEXT: # %bb.7: # %bb11
27+
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
28+
; CHECK-NEXT: testq %rcx, %rcx
29+
; CHECK-NEXT: jns .LBB0_2
30+
; CHECK-NEXT: jmp .LBB0_5
31+
; CHECK-NEXT: .LBB0_3: # %bb10
32+
; CHECK-NEXT: xorl %ecx, %ecx
33+
; CHECK-NEXT: testb %cl, %cl
34+
; CHECK-NEXT: jne .LBB0_5
35+
; CHECK-NEXT: .p2align 4
36+
; CHECK-NEXT: .LBB0_4: # %bb12
37+
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
38+
; CHECK-NEXT: cmpq $1, %rax
39+
; CHECK-NEXT: jg .LBB0_4
40+
; CHECK-NEXT: jmp .LBB0_5
41+
entry:
42+
%i = load i32, ptr %arg, align 4
43+
%i2 = sext i32 %i to i64
44+
%i3 = load i32, ptr %arg1, align 4
45+
%i4 = sext i32 %i3 to i64
46+
%i5 = sub nsw i64 %i4, %i2
47+
%i6 = add nsw i64 %i5, 1
48+
%i7 = icmp sgt i64 %i5, -1
49+
br i1 %i7, label %bb, label %bb10
50+
51+
bb: ; preds = %bb, %entry
52+
%i8 = phi i64 [ %i6, %entry ], [ poison, %bb ]
53+
%i9 = icmp sgt i64 %i8, 1
54+
br i1 %i9, label %bb, label %bb16
55+
56+
bb10: ; preds = %bb11, %entry
57+
switch i32 poison, label %bb16 [
58+
i32 1, label %bb11
59+
i32 2, label %bb12
60+
]
61+
62+
bb11: ; preds = %bb10
63+
br i1 %i7, label %bb10, label %bb16
64+
65+
bb12: ; preds = %bb14, %bb10
66+
%i13 = phi i64 [ poison, %bb14 ], [ %i6, %bb10 ]
67+
br label %bb14
68+
69+
bb14: ; preds = %bb12
70+
%i15 = icmp sgt i64 %i13, 1
71+
br i1 %i15, label %bb12, label %bb16
72+
73+
bb16: ; preds = %bb14, %bb11, %bb10, %bb
74+
ret void
75+
}

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