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tonykuttaitonykuttai
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Modified the shrink-wrap-frame-pointer.ll and removed the return statement is check in shrinkwrap.cpp
1 parent f57b233 commit bd0fb18

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2 files changed

+71
-78
lines changed

2 files changed

+71
-78
lines changed

‎llvm/lib/CodeGen/ShrinkWrap.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -355,7 +355,7 @@ bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS,
355355
RCI.getLastCalleeSavedAlias(PhysReg) ||
356356
(!MI.isReturn() &&
357357
TRI->isNonallocatableRegisterCalleeSave(PhysReg)) ||
358-
(!MI.isReturn() && TRI->isVirtualFrameRegister(PhysReg));
358+
TRI->isVirtualFrameRegister(PhysReg);
359359
} else if (MO.isRegMask()) {
360360
// Check if this regmask clobbers any of the CSRs.
361361
for (unsigned Reg : getCurrentCSRs(RS)) {

‎llvm/test/CodeGen/PowerPC/shrink-wrap-frame-pointer.ll‎

Lines changed: 70 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -1,103 +1,96 @@
1-
; Test file to check shrink-wrap pass
1+
; Test file to verify the prologue and epilogue insertion point computation by the shrink-wrap pass
22

3+
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC64
34
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC32-AIX
45
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 | FileCheck %s --check-prefixes=POWERPC64-AIX
56

6-
@.str = private unnamed_addr constant [50 x i8] c"parent_frame_pointer > __builtin_frame_address(0)\00", align 1
7-
@.str.1 = private unnamed_addr constant [8 x i8] c"bad.cpp\00", align 1
7+
define void @foo(ptr noundef readnone %parent_frame_pointer) {
8+
; POWERPC64-LABEL: foo
9+
; POWERPC64: # %bb.0:
10+
; POWERPC64: mflr [[LR:[0-9]+]]
11+
; POWERPC64-NEXT: stdu 1, -32(1)
12+
; POWERPC64-NEXT: std [[LR]], 48(1)
13+
; POWERPC64: cmpld [[REG1:[0-9]+]], 1
14+
; POWERPC64: # %bb.1:
15+
; POWERPC64-NEXT: addi 1, 1, 32
16+
; POWERPC64-NEXT: ld [[LR]], 16(1)
17+
; POWERPC64-NEXT: mtlr [[LR]]
18+
; POWERPC64-NEXT: blr
819

9-
; Function Attrs: mustprogress noinline nounwind
10-
define void @_Z3fooPv(ptr noundef readnone %parent_frame_pointer) local_unnamed_addr #0 {
20+
; POWERPC32-AIX-LABEL: .foo:
21+
; POWERPC32-AIX: # %bb.0:
22+
; POWERPC32-AIX-NEXT: mflr [[LR:[0-9]+]]
23+
; POWERPC32-AIX-NEXT: stwu 1, -64(1)
24+
; POWERPC32-AIX-NEXT: cmplw [[REG1:[0-9]+]], 1
25+
; POWERPC32-AIX: # %bb.1:
26+
; POWERPC32-AIX-NEXT: addi 1, 1, 64
27+
; POWERPC32-AIX-NEXT: lwz [[LR]], 8(1)
28+
; POWERPC32-AIX-NEXT: mtlr [[LR]]
29+
; POWERPC32-AIX-NEXT: blr
1130

12-
; POWERPC32-AIX-LABEL: ._Z3fooPv:
13-
; POWERPC32-AIX: # %bb.0:
14-
; POWERPC32-AIX-NEXT: mflr 0
15-
; POWERPC32-AIX-NEXT: stwu 1, -64(1)
16-
; POWERPC32-AIX-NEXT: cmplw 3, 1
17-
; POWERPC32-AIX-NEXT: stw 0, 72(1)
18-
; POWERPC32-AIX-NEXT: ble- 0, L..BB0_2
19-
; POWERPC32-AIX-NEXT: # %bb.1:
20-
; POWERPC32-AIX-NEXT: addi 1, 1, 64
21-
; POWERPC32-AIX-NEXT: lwz 0, 8(1)
22-
; POWERPC32-AIX-NEXT: mtlr 0
23-
; POWERPC32-AIX-NEXT: blr
24-
; POWERPC32-AIX-NEXT: L..BB0_2:
25-
; POWERPC32-AIX-NEXT: lwz 4, L..C0(2)
26-
; POWERPC32-AIX-NEXT: li 5, 6
27-
; POWERPC32-AIX-NEXT: addi 3, 4, 8
28-
; POWERPC32-AIX-NEXT: bl .__assert[PR]
29-
; POWERPC32-AIX-NEXT: nop
30-
31-
; POWERPC64-AIX-LABEL: ._Z3fooPv:
32-
; POWERPC64-AIX: # %bb.0:
33-
; POWERPC64-AIX-NEXT: mflr 0
34-
; POWERPC64-AIX-NEXT: stdu 1, -112(1)
35-
; POWERPC64-AIX-NEXT: cmpld 3, 1
36-
; POWERPC64-AIX-NEXT: std 0, 128(1)
37-
; POWERPC64-AIX-NEXT: ble- 0, L..BB0_2
38-
; POWERPC64-AIX-NEXT: # %bb.1:
39-
; POWERPC64-AIX-NEXT: addi 1, 1, 112
40-
; POWERPC64-AIX-NEXT: ld 0, 16(1)
41-
; POWERPC64-AIX-NEXT: mtlr 0
42-
; POWERPC64-AIX-NEXT: blr
43-
; POWERPC64-AIX-NEXT: L..BB0_2:
44-
; POWERPC64-AIX-NEXT: ld 4, L..C0(2)
45-
; POWERPC64-AIX-NEXT: li 5, 6
46-
; POWERPC64-AIX-NEXT: addi 3, 4, 8
47-
; POWERPC64-AIX-NEXT: bl .__assert[PR]
48-
; POWERPC64-AIX-NEXT: nop
31+
; POWERPC64-AIX-LABEL: .foo:
32+
; POWERPC64-AIX: # %bb.0:
33+
; POWERPC64-AIX-NEXT: mflr [[LR:[0-9]+]]
34+
; POWERPC64-AIX-NEXT: stdu 1, -112(1)
35+
; POWERPC64-AIX-NEXT: cmpld [[REG1:[0-9]+]], 1
36+
; POWERPC64-AIX: # %bb.1:
37+
; POWERPC64-AIX-NEXT: addi 1, 1, 112
38+
; POWERPC64-AIX-NEXT: ld [[LR]], 16(1)
39+
; POWERPC64-AIX-NEXT: mtlr [[LR]]
40+
; POWERPC64-AIX-NEXT: blr
4941

5042
entry:
51-
%0 = tail call ptr @llvm.frameaddress.p0(i32 0)
52-
%cmp = icmp ugt ptr %parent_frame_pointer, %0
43+
%frameaddress = tail call ptr @llvm.frameaddress.p0(i32 0)
44+
%cmp = icmp ugt ptr %parent_frame_pointer, %frameaddress
5345
br i1 %cmp, label %cond.end, label %cond.false
5446

5547
cond.false: ; preds = %entry
56-
tail call void @__assert(ptr noundef nonnull @.str, ptr noundef nonnull @.str.1, i32 noundef 6) #4
48+
tail call void @abort()
5749
unreachable
5850

5951
cond.end: ; preds = %entry
6052
ret void
6153
}
6254

63-
; Function Attrs: mustprogress nocallback nofree nosync nounwind willreturn memory(none)
64-
declare ptr @llvm.frameaddress.p0(i32 immarg) #1
55+
declare ptr @llvm.frameaddress.p0(i32 immarg)
56+
declare void @abort()
6557

66-
; Function Attrs: noreturn nounwind
67-
declare void @__assert(ptr noundef, ptr noundef, i32 noundef) local_unnamed_addr #2
58+
define noundef i32 @main() {
59+
; POWERPC64-LABEL: main
60+
; POWERPC64: # %bb.0:
61+
; POWERPC64-NEXT: mflr [[LR:[0-9]+]]
62+
; POWERPC64-NEXT: stdu 1, -32(1)
63+
; POWERPC64-NEXT: std [[LR]], 48(1)
64+
; POWERPC64: mr [[REG2:[0-9]+]], 1
65+
; POWERPC64: addi 1, 1, 32
66+
; POWERPC64-NEXT: ld [[LR]], 16(1)
67+
; POWERPC64-NEXT: mtlr [[LR]]
68+
; POWERPC64-NEXT: blr
6869

69-
; Function Attrs: mustprogress norecurse nounwind
70-
define noundef i32 @main() local_unnamed_addr #3 {
71-
; POWERPC32-AIX-LABEL: .main:
72-
; POWERPC32-AIX: # %bb.0:
73-
; POWERPC32-AIX-NEXT: mflr 0
74-
; POWERPC32-AIX-NEXT: stwu 1, -64(1)
75-
; POWERPC32-AIX-NEXT: mr 3, 1
76-
; POWERPC32-AIX-NEXT: stw 0, 72(1)
77-
; POWERPC32-AIX-NEXT: bl ._Z3fooPv
78-
; POWERPC32-AIX-NEXT: nop
79-
; POWERPC32-AIX-NEXT: li 3, 0
80-
; POWERPC32-AIX-NEXT: addi 1, 1, 64
81-
; POWERPC32-AIX-NEXT: lwz 0, 8(1)
82-
; POWERPC32-AIX-NEXT: mtlr 0
83-
; POWERPC32-AIX-NEXT: blr
70+
; POWERPC32-AIX-LABEL: .main:
71+
; POWERPC32-AIX: # %bb.0:
72+
; POWERPC32-AIX-NEXT: mflr [[LR:[0-9]+]]
73+
; POWERPC32-AIX-NEXT: stwu 1, -64(1)
74+
; POWERPC32-AIX-NEXT: mr [[REG2:[0-9]+]], 1
75+
; POWERPC32-AIX-NEXT: stw [[LR]], 72(1)
76+
; POWERPC32-AIX: addi 1, 1, 64
77+
; POWERPC32-AIX-NEXT: lwz [[LR]], 8(1)
78+
; POWERPC32-AIX-NEXT: mtlr [[LR]]
79+
; POWERPC32-AIX-NEXT: blr
8480

8581
; POWERPC64-AIX-LABEL: .main:
8682
; POWERPC64-AIX: # %bb.0:
87-
; POWERPC64-AIX-NEXT: mflr 0
88-
; POWERPC64-AIX-NEXT: stdu 1, -112(1)
89-
; POWERPC64-AIX-NEXT: mr 3, 1
90-
; POWERPC64-AIX-NEXT: std 0, 128(1)
91-
; POWERPC64-AIX-NEXT: bl ._Z3fooPv
92-
; POWERPC64-AIX-NEXT: nop
93-
; POWERPC64-AIX-NEXT: li 3, 0
94-
; POWERPC64-AIX-NEXT: addi 1, 1, 112
95-
; POWERPC64-AIX-NEXT: ld 0, 16(1)
96-
; POWERPC64-AIX-NEXT: mtlr 0
97-
; POWERPC64-AIX-NEXT: blr
83+
; POWERPC64-AIX-NEXT: mflr [[LR:[0-9]+]]
84+
; POWERPC64-AIX-NEXT: stdu 1, -112(1)
85+
; POWERPC64-AIX-NEXT: mr [[REG2:[0-9]+]], 1
86+
; POWERPC64-AIX-NEXT: std [[LR]], 128(1)
87+
; POWERPC64-AIX: addi 1, 1, 112
88+
; POWERPC64-AIX-NEXT: ld [[LR]], 16(1)
89+
; POWERPC64-AIX-NEXT: mtlr [[LR]]
90+
; POWERPC64-AIX-NEXT: blr
9891

9992
entry:
100-
%0 = tail call ptr @llvm.frameaddress.p0(i32 0)
101-
tail call void @_Z3fooPv(ptr noundef %0)
93+
%frameaddress = tail call ptr @llvm.frameaddress.p0(i32 0)
94+
tail call void @foo(ptr noundef %frameaddress)
10295
ret i32 0
10396
}

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