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gandhi56gandhi56
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Improve tests
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4 files changed

+171
-105
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.mir‎

Lines changed: 91 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,13 @@ body: |
1818
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s16)
1919
; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[ANYEXT]], [[ANYEXT1]]
2020
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[ADD]](s32)
21-
; CHECK-NEXT: S_ENDPGM 0, implicit [[TRUNC2]](s16)
21+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s16) = G_AND [[TRUNC2]], [[TRUNC2]]
2222
%0:_(s32) = COPY $sgpr0
2323
%1:_(s32) = COPY $sgpr1
2424
%2:_(s16) = G_TRUNC %0
2525
%3:_(s16) = G_TRUNC %1
2626
%4:_(s16) = G_ADD %2, %3
27-
S_ENDPGM 0, implicit %4
27+
%5:_(s16) = G_AND %4, %4
2828
...
2929

3030
---
@@ -43,13 +43,13 @@ body: |
4343
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
4444
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
4545
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s16) = G_ADD [[COPY2]], [[TRUNC1]]
46-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s16)
46+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[ADD]], [[ADD]]
4747
%0:_(s32) = COPY $sgpr0
4848
%1:_(s32) = COPY $vgpr0
4949
%2:_(s16) = G_TRUNC %0
5050
%3:_(s16) = G_TRUNC %1
5151
%4:_(s16) = G_ADD %2, %3
52-
S_ENDPGM 0, implicit %4
52+
%5:_(s16) = G_AND %4, %4
5353
...
5454

5555
---
@@ -68,13 +68,13 @@ body: |
6868
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
6969
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC1]](s16)
7070
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s16) = G_ADD [[TRUNC]], [[COPY2]]
71-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s16)
71+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[ADD]], [[ADD]]
7272
%0:_(s32) = COPY $vgpr0
7373
%1:_(s32) = COPY $sgpr0
7474
%2:_(s16) = G_TRUNC %0
7575
%3:_(s16) = G_TRUNC %1
7676
%4:_(s16) = G_ADD %2, %3
77-
S_ENDPGM 0, implicit %4
77+
%5:_(s16) = G_AND %4, %4
7878
...
7979

8080
---
@@ -92,13 +92,13 @@ body: |
9292
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
9393
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
9494
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s16) = G_ADD [[TRUNC]], [[TRUNC1]]
95-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s16)
95+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s16) = G_AND [[ADD]], [[ADD]]
9696
%0:_(s32) = COPY $vgpr0
9797
%1:_(s32) = COPY $vgpr1
9898
%2:_(s16) = G_TRUNC %0
9999
%3:_(s16) = G_TRUNC %1
100100
%4:_(s16) = G_ADD %2, %3
101-
S_ENDPGM 0, implicit %4
101+
%5:_(s16) = G_AND %4, %4
102102
...
103103

104104
---
@@ -114,11 +114,11 @@ body: |
114114
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
115115
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
116116
; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[COPY]], [[COPY1]]
117-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
117+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ADD]], [[ADD]]
118118
%0:_(s32) = COPY $sgpr0
119119
%1:_(s32) = COPY $sgpr1
120120
%2:_(s32) = G_ADD %0, %1
121-
S_ENDPGM 0, implicit %2
121+
%3:_(s32) = G_AND %2, %2
122122
...
123123

124124
---
@@ -135,11 +135,11 @@ body: |
135135
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
136136
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
137137
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY2]], [[COPY1]]
138-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
138+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ADD]], [[ADD]]
139139
%0:_(s32) = COPY $sgpr0
140140
%1:_(s32) = COPY $vgpr0
141141
%2:_(s32) = G_ADD %0, %1
142-
S_ENDPGM 0, implicit %2
142+
%3:_(s32) = G_AND %2, %2
143143
...
144144

145145
---
@@ -156,11 +156,11 @@ body: |
156156
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
157157
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
158158
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY2]]
159-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
159+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ADD]], [[ADD]]
160160
%0:_(s32) = COPY $vgpr0
161161
%1:_(s32) = COPY $sgpr0
162162
%2:_(s32) = G_ADD %0, %1
163-
S_ENDPGM 0, implicit %2
163+
%3:_(s32) = G_AND %2, %2
164164
...
165165

166166
---
@@ -176,11 +176,11 @@ body: |
176176
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
177177
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
178178
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[COPY]], [[COPY1]]
179-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s32)
179+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ADD]], [[ADD]]
180180
%0:_(s32) = COPY $vgpr0
181181
%1:_(s32) = COPY $vgpr1
182182
%2:_(s32) = G_ADD %0, %1
183-
S_ENDPGM 0, implicit %2
183+
%3:_(s32) = G_AND %2, %2
184184
...
185185

186186
---
@@ -196,11 +196,13 @@ body: |
196196
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
197197
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr3
198198
; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s64) = G_ADD [[COPY]], [[COPY1]]
199-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
199+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 255
200+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s64) = G_AND [[ADD]], [[ADD]]
200201
%0:_(s64) = COPY $sgpr0_sgpr1
201202
%1:_(s64) = COPY $sgpr2_sgpr3
202203
%2:_(s64) = G_ADD %0, %1
203-
S_ENDPGM 0, implicit %2
204+
%3:_(s64) = G_CONSTANT i64 255
205+
%4:_(s64) = G_AND %2, %2
204206
...
205207

206208
---
@@ -217,11 +219,15 @@ body: |
217219
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
218220
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
219221
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s64) = G_ADD [[COPY2]], [[COPY1]]
220-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
222+
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
223+
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
224+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]
225+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]
226+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
221227
%0:_(s64) = COPY $sgpr0_sgpr1
222228
%1:_(s64) = COPY $vgpr0_vgpr1
223229
%2:_(s64) = G_ADD %0, %1
224-
S_ENDPGM 0, implicit %2
230+
%3:_(s64) = G_AND %2, %2
225231
...
226232

227233
---
@@ -238,11 +244,15 @@ body: |
238244
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
239245
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s64) = COPY [[COPY1]](s64)
240246
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s64) = G_ADD [[COPY]], [[COPY2]]
241-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
247+
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
248+
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
249+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]
250+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]
251+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
242252
%0:_(s64) = COPY $vgpr0_vgpr1
243253
%1:_(s64) = COPY $sgpr0_sgpr1
244254
%2:_(s64) = G_ADD %0, %1
245-
S_ENDPGM 0, implicit %2
255+
%3:_(s64) = G_AND %2, %2
246256
...
247257

248258
---
@@ -258,11 +268,15 @@ body: |
258268
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
259269
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
260270
; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s64) = G_ADD [[COPY]], [[COPY1]]
261-
; CHECK-NEXT: S_ENDPGM 0, implicit [[ADD]](s64)
271+
; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
272+
; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ADD]](s64)
273+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]
274+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]
275+
; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
262276
%0:_(s64) = COPY $vgpr0_vgpr1
263277
%1:_(s64) = COPY $vgpr2_vgpr3
264278
%2:_(s64) = G_ADD %0, %1
265-
S_ENDPGM 0, implicit %2
279+
%3:_(s64) = G_AND %2, %2
266280
...
267281

268282
---
@@ -278,11 +292,16 @@ body: |
278292
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
279293
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
280294
; CHECK-NEXT: [[UADDO:%[0-9]+]]:sgpr(s32), [[UADDO1:%[0-9]+]]:sgpr(s32) = G_UADDO [[COPY]], [[COPY1]]
281-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
295+
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
296+
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[UADDO1]], [[C]]
297+
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
298+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND]](s32), [[C]], [[C1]]
299+
; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[SELECT]], [[UADDO]]
282300
%0:_(s32) = COPY $sgpr0
283301
%1:_(s32) = COPY $sgpr1
284302
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
285-
S_ENDPGM 0, implicit %2
303+
%4:_(s32) = G_ZEXT %3
304+
%5:_(s32) = G_AND %4, %2
286305
...
287306

288307
---
@@ -299,11 +318,15 @@ body: |
299318
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
300319
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
301320
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY2]], [[COPY1]]
302-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
321+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
322+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
323+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[UADDO1]](s1), [[C]], [[C1]]
324+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDO]], [[SELECT]]
303325
%0:_(s32) = COPY $sgpr0
304326
%1:_(s32) = COPY $vgpr1
305327
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
306-
S_ENDPGM 0, implicit %2
328+
%4:_(s32) = G_ZEXT %3
329+
%5:_(s32) = G_AND %2, %4
307330
...
308331

309332
---
@@ -320,11 +343,15 @@ body: |
320343
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
321344
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
322345
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY2]]
323-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
346+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
347+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
348+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[UADDO1]](s1), [[C]], [[C1]]
349+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDO]], [[SELECT]]
324350
%0:_(s32) = COPY $vgpr0
325351
%1:_(s32) = COPY $sgpr1
326352
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
327-
S_ENDPGM 0, implicit %2
353+
%4:_(s32) = G_ZEXT %3
354+
%5:_(s32) = G_AND %2, %4
328355
...
329356

330357
---
@@ -340,11 +367,15 @@ body: |
340367
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
341368
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
342369
; CHECK-NEXT: [[UADDO:%[0-9]+]]:vgpr(s32), [[UADDO1:%[0-9]+]]:vcc(s1) = G_UADDO [[COPY]], [[COPY1]]
343-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDO]](s32)
370+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
371+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
372+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[UADDO1]](s1), [[C]], [[C1]]
373+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDO]], [[SELECT]]
344374
%0:_(s32) = COPY $vgpr0
345375
%1:_(s32) = COPY $vgpr1
346376
%2:_(s32), %3:_(s1) = G_UADDO %0, %1
347-
S_ENDPGM 0, implicit %2
377+
%4:_(s32) = G_ZEXT %3
378+
%5:_(s32) = G_AND %2, %4
348379
...
349380

350381
---
@@ -363,13 +394,17 @@ body: |
363394
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
364395
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[C]]
365396
; CHECK-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
366-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
397+
; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[UADDE1]], [[C]]
398+
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
399+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND1]](s32), [[C]], [[C1]]
400+
; CHECK-NEXT: [[AND2:%[0-9]+]]:sgpr(s32) = G_AND [[UADDE]], [[SELECT]]
367401
%0:_(s32) = COPY $sgpr0
368402
%1:_(s32) = COPY $sgpr1
369403
%2:_(s32) = COPY $sgpr2
370404
%3:_(s1) = G_TRUNC %2
371405
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
372-
S_ENDPGM 0, implicit %4
406+
%6:_(s32) = G_ZEXT %5
407+
%7:_(s32) = G_AND %4, %6
373408
...
374409

375410
---
@@ -388,13 +423,17 @@ body: |
388423
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
389424
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32)
390425
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY3]], [[COPY1]], [[AMDGPU_COPY_VCC_SCC]]
391-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
426+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
427+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
428+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[UADDE1]](s1), [[C]], [[C1]]
429+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDE]], [[SELECT]]
392430
%0:_(s32) = COPY $sgpr0
393431
%1:_(s32) = COPY $vgpr1
394432
%2:_(s32) = COPY $sgpr2
395433
%3:_(s1) = G_TRUNC %2
396434
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
397-
S_ENDPGM 0, implicit %4
435+
%6:_(s32) = G_ZEXT %5
436+
%7:_(s32) = G_AND %4, %6
398437
...
399438

400439
---
@@ -413,13 +452,17 @@ body: |
413452
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
414453
; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[COPY2]](s32)
415454
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY3]], [[AMDGPU_COPY_VCC_SCC]]
416-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
455+
; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1
456+
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
457+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[UADDE1]](s1), [[C]], [[C1]]
458+
; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UADDE]], [[SELECT]]
417459
%0:_(s32) = COPY $vgpr0
418460
%1:_(s32) = COPY $sgpr1
419461
%2:_(s32) = COPY $sgpr2
420462
%3:_(s1) = G_TRUNC %2
421463
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
422-
S_ENDPGM 0, implicit %4
464+
%6:_(s32) = G_ZEXT %5
465+
%7:_(s32) = G_AND %4, %6
423466
...
424467

425468
---
@@ -440,13 +483,15 @@ body: |
440483
; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0
441484
; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]
442485
; CHECK-NEXT: [[UADDE:%[0-9]+]]:vgpr(s32), [[UADDE1:%[0-9]+]]:vcc(s1) = G_UADDE [[COPY]], [[COPY1]], [[ICMP]]
443-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
486+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[UADDE1]](s1), [[C]], [[C1]]
487+
; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UADDE]], [[SELECT]]
444488
%0:_(s32) = COPY $vgpr0
445489
%1:_(s32) = COPY $vgpr1
446490
%2:_(s32) = COPY $vgpr2
447491
%3:_(s1) = G_TRUNC %2
448492
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
449-
S_ENDPGM 0, implicit %4
493+
%6:_(s32) = G_ZEXT %5
494+
%7:_(s32) = G_AND %4, %6
450495
...
451496

452497
---
@@ -465,12 +510,15 @@ body: |
465510
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1
466511
; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY2]], [[C]]
467512
; CHECK-NEXT: [[UADDE:%[0-9]+]]:sgpr(s32), [[UADDE1:%[0-9]+]]:sgpr(s32) = G_UADDE [[COPY]], [[COPY1]], [[AND]]
468-
; CHECK-NEXT: S_ENDPGM 0, implicit [[UADDE]](s32)
513+
; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[UADDE1]], [[C]]
514+
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
515+
; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND1]](s32), [[C]], [[C1]]
516+
; CHECK-NEXT: [[AND2:%[0-9]+]]:sgpr(s32) = G_AND [[UADDE]], [[SELECT]]
469517
%0:_(s32) = COPY $sgpr0
470518
%1:_(s32) = COPY $sgpr1
471519
%2:_(s32) = COPY $sgpr2
472520
%3:_(s1) = G_TRUNC %2
473521
%4:_(s32), %5:_(s1) = G_UADDE %0, %1, %3
474-
%6:_(s32) = G_ANYEXT %5:_(s1)
475-
S_ENDPGM 0, implicit %4
522+
%6:_(s32) = G_ZEXT %5
523+
%8:_(s32) = G_AND %4, %6
476524
...

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