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[RISCV] Improve error for using x18-x27 in a register list with RVE. (#133936)
matchRegisterNameHelper returns MCRegister() for RVE so the first RVE check was dead. For the second check, I've moved the RVE check from the comma parsing to the identifier parsing so the diagnostic points at the register. Note we're using matchRegisterName instead of matchRegisterNameHelper to avoid allowing ABI names so we don't get the RVE check that lives inside matchRegisterNameHelper. The errors for RVE in general should probably say something other than "invalid register", but that's a problem throughout the assembler.
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6 files changed

+46
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‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 26 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -2577,7 +2577,7 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
25772577
if (parseToken(AsmToken::LCurly, "register list must start with '{'"))
25782578
return ParseStatus::Failure;
25792579

2580-
bool IsEABI = isRVE();
2580+
bool IsRVE = isRVE();
25812581

25822582
if (getLexer().isNot(AsmToken::Identifier))
25832583
return Error(getLoc(), "register list must start from 'ra' or 'x1'");
@@ -2617,46 +2617,41 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
26172617
// parse case like -s1
26182618
if (parseOptionalToken(AsmToken::Minus)) {
26192619
StringRef EndName = getLexer().getTok().getIdentifier();
2620-
// FIXME: the register mapping and checks of EABI is wrong
2620+
// FIXME: the register mapping and checks of RVE is wrong
26212621
RegEnd = matchRegisterNameHelper(EndName);
26222622
if (!(RegEnd == RISCV::X9 ||
26232623
(RegEnd >= RISCV::X18 && RegEnd <= RISCV::X27)))
26242624
return Error(getLoc(), "invalid register");
2625-
if (IsEABI && RegEnd != RISCV::X9)
2626-
return Error(getLoc(), "contiguous register list of EABI can only be "
2627-
"'s0-s1' or 'x8-x9' pair");
26282625
getLexer().Lex();
26292626
}
26302627

2631-
if (!IsEABI) {
2632-
// parse extra part like ', x18[-x20]' for XRegList
2633-
if (parseOptionalToken(AsmToken::Comma)) {
2634-
if (RegEnd != RISCV::X9)
2635-
return Error(
2636-
getLoc(),
2637-
"first contiguous registers pair of register list must be 'x8-x9'");
2628+
// parse extra part like ', x18[-x20]' for XRegList
2629+
if (parseOptionalToken(AsmToken::Comma)) {
2630+
if (RegEnd != RISCV::X9)
2631+
return Error(
2632+
getLoc(),
2633+
"first contiguous registers pair of register list must be 'x8-x9'");
26382634

2639-
// parse ', x18' for extra part
2640-
if (getLexer().isNot(AsmToken::Identifier))
2635+
// parse ', x18' for extra part
2636+
if (getLexer().isNot(AsmToken::Identifier) || IsRVE)
2637+
return Error(getLoc(), "invalid register");
2638+
StringRef EndName = getLexer().getTok().getIdentifier();
2639+
RegEnd = MatchRegisterName(EndName);
2640+
if (RegEnd != RISCV::X18)
2641+
return Error(getLoc(),
2642+
"second contiguous registers pair of register list "
2643+
"must start from 'x18'");
2644+
getLexer().Lex();
2645+
2646+
// parse '-x20' for extra part
2647+
if (parseOptionalToken(AsmToken::Minus)) {
2648+
if (getLexer().isNot(AsmToken::Identifier) || IsRVE)
26412649
return Error(getLoc(), "invalid register");
2642-
StringRef EndName = getLexer().getTok().getIdentifier();
2650+
EndName = getLexer().getTok().getIdentifier();
26432651
RegEnd = MatchRegisterName(EndName);
2644-
if (RegEnd != RISCV::X18)
2645-
return Error(getLoc(),
2646-
"second contiguous registers pair of register list "
2647-
"must start from 'x18'");
2652+
if (!(RegEnd >= RISCV::X19 && RegEnd <= RISCV::X27))
2653+
return Error(getLoc(), "invalid register");
26482654
getLexer().Lex();
2649-
2650-
// parse '-x20' for extra part
2651-
if (parseOptionalToken(AsmToken::Minus)) {
2652-
if (getLexer().isNot(AsmToken::Identifier))
2653-
return Error(getLoc(), "invalid register");
2654-
EndName = getLexer().getTok().getIdentifier();
2655-
RegEnd = MatchRegisterName(EndName);
2656-
if (!(RegEnd >= RISCV::X19 && RegEnd <= RISCV::X27))
2657-
return Error(getLoc(), "invalid register");
2658-
getLexer().Lex();
2659-
}
26602655
}
26612656
}
26622657

@@ -2667,7 +2662,7 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
26672662
if (parseToken(AsmToken::RCurly, "register list must end with '}'"))
26682663
return ParseStatus::Failure;
26692664

2670-
auto Encode = RISCVZC::encodeRlist(RegEnd, IsEABI);
2665+
auto Encode = RISCVZC::encodeRlist(RegEnd, IsRVE);
26712666
assert(Encode != RISCVZC::INVALID_RLIST);
26722667
if (MustIncludeS0)
26732668
assert(Encode != RISCVZC::RA);

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -603,8 +603,8 @@ enum RLISTENCODE {
603603
INVALID_RLIST,
604604
};
605605

606-
inline unsigned encodeRlist(MCRegister EndReg, bool IsRV32E = false) {
607-
assert((!IsRV32E || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
606+
inline unsigned encodeRlist(MCRegister EndReg, bool IsRVE = false) {
607+
assert((!IsRVE || EndReg <= RISCV::X9) && "Invalid Rlist for RV32E");
608608
switch (EndReg) {
609609
case RISCV::X1:
610610
return RLISTENCODE::RA;

‎llvm/test/MC/RISCV/rv32e-xqccmp-invalid.s‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,11 @@ qc.cm.push {ra,s0-s2}, -16
1414
# CHECK: :[[@LINE+1]]:21: error: invalid register
1515
qc.cm.popret {ra,s0-s2}, 16
1616
# CHECK-DIS: ba72 <unknown>
17-
# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
17+
# CHECK: :[[@LINE+1]]:23: error: invalid register
1818
qc.cm.pop {x1, x8-x9, x18}, 16
1919
# CHECK-DIS: b972 <unknown>
20-
# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
20+
# CHECK: :[[@LINE+1]]:26: error: invalid register
2121
qc.cm.pushfp {x1, x8-x9, x18}, -16
22+
# CHECK-DIS: b972 <unknown>
23+
# CHECK: :[[@LINE+1]]:22: error: invalid register
24+
qc.cm.pushfp {ra, s0-s2}, -16

‎llvm/test/MC/RISCV/rv32e-zcmp-invalid.s‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,5 +14,8 @@ cm.push {ra,s0-s2}, -16
1414
# CHECK: :[[@LINE+1]]:18: error: invalid register
1515
cm.popret {ra,s0-s2}, 16
1616
# CHECK-DIS: ba72 <unknown>
17-
# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
17+
# CHECK: :[[@LINE+1]]:20: error: invalid register
1818
cm.pop {x1, x8-x9, x18}, 16
19+
# CHECK-DIS: ba72 <unknown>
20+
# CHECK: :[[@LINE+1]]:16: error: invalid register
21+
cm.pop {ra, s0-s2}, 16

‎llvm/test/MC/RISCV/rv64e-xqccmp-invalid.s‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,11 @@ qc.cm.push {ra,s0-s2}, -32
1414
# CHECK: :[[@LINE+1]]:21: error: invalid register
1515
qc.cm.popret {ra,s0-s2}, 32
1616
# CHECK-DIS: ba72 <unknown>
17-
# CHECK: :[[@LINE+1]]:21: error: register list must end with '}'
17+
# CHECK: :[[@LINE+1]]:23: error: invalid register
1818
qc.cm.pop {x1, x8-x9, x18}, 32
1919
# CHECK-DIS: b972 <unknown>
20-
# CHECK: :[[@LINE+1]]:24: error: register list must end with '}'
20+
# CHECK: :[[@LINE+1]]:26: error: invalid register
2121
qc.cm.pushfp {x1, x8-x9, x18}, -32
22+
# CHECK-DIS: b972 <unknown>
23+
# CHECK: :[[@LINE+1]]:22: error: invalid register
24+
qc.cm.pushfp {ra, s0-s2}, -32

‎llvm/test/MC/RISCV/rv64e-zcmp-invalid.s‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,5 +14,8 @@ cm.push {ra,s0-s2}, -32
1414
# CHECK: :[[@LINE+1]]:18: error: invalid register
1515
cm.popret {ra,s0-s2}, 32
1616
# CHECK-DIS: ba72 <unknown>
17-
# CHECK: :[[@LINE+1]]:18: error: register list must end with '}'
17+
# CHECK: :[[@LINE+1]]:20: error: invalid register
1818
cm.pop {x1, x8-x9, x18}, 32
19+
# CHECK-DIS: ba72 <unknown>
20+
# CHECK: :[[@LINE+1]]:16: error: invalid register
21+
cm.pop {ra, s0-s2}, 32

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