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[AMDGPU][GlobalISel] Add register bank legalization for G_AMDGPU_BUFFER_LOAD_BYTE_AND_SHORT
Added new test file.
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6 files changed

+271
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lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -894,6 +894,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
894894
.Div(B128, {{VgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}})
895895
.Uni(B128, {{UniInVgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}});
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addRulesForGOpcs({G_AMDGPU_BUFFER_LOAD_USHORT, G_AMDGPU_BUFFER_LOAD_UBYTE,
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G_AMDGPU_BUFFER_LOAD_SSHORT, G_AMDGPU_BUFFER_LOAD_SBYTE},
899+
StandardB)
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.Div(B32, {{VgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}})
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.Uni(B32, {{UniInVgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}});
902+
897903
addRulesForGOpcs({G_AMDGPU_BUFFER_STORE})
898904
.Any({{S32}, {{}, {Vgpr32, SgprV4S32, Vgpr32, Vgpr32, Sgpr32}}});
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll‎

Lines changed: 257 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,257 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s
3+
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define amdgpu_ps void @test_buffer_load_u8_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_u8_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
8+
; GFX12-NEXT: s_mov_b32 s10, s7
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; GFX12-NEXT: s_mov_b32 s11, s8
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; GFX12-NEXT: buffer_load_u8 v0, v0, s[0:3], s5 offen
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s6
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: global_store_b32 v1, v0, s[10:11]
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; GFX12-NEXT: s_endpgm
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%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
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%zext = zext i8 %val to i32
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%result = add i32 %zext, %addend
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_buffer_load_i8_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_i8_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
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; GFX12-NEXT: s_mov_b32 s10, s7
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; GFX12-NEXT: s_mov_b32 s11, s8
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; GFX12-NEXT: buffer_load_i8 v0, v0, s[0:3], s5 offen
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s6
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: global_store_b32 v1, v0, s[10:11]
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; GFX12-NEXT: s_endpgm
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%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
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%sext = sext i8 %val to i32
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%result = add i32 %sext, %addend
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_buffer_load_u16_uniform(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_u16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: buffer_load_u16 v0, off, s[0:3], s4
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; GFX12-NEXT: v_mov_b32_e32 v1, 0
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s5
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: global_store_b32 v1, v0, s[6:7]
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; GFX12-NEXT: s_endpgm
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%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
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%zext = zext i16 %val to i32
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%result = add i32 %zext, %addend
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_buffer_load_i16_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_i16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
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; GFX12-NEXT: s_mov_b32 s10, s7
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; GFX12-NEXT: s_mov_b32 s11, s8
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; GFX12-NEXT: buffer_load_i16 v0, v0, s[0:3], null offen
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_readfirstlane_b32 s0, v0
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; GFX12-NEXT: s_add_co_i32 s0, s0, s6
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: global_store_b32 v1, v0, s[10:11]
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; GFX12-NEXT: s_endpgm
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%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
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%sext = sext i16 %val to i32
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%result = add i32 %sext, %addend
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store i32 %result, ptr addrspace(1) %out
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ret void
84+
}
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define amdgpu_ps void @test_buffer_load_u8_divergent(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_u8_divergent:
88+
; GFX12: ; %bb.0:
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; GFX12-NEXT: buffer_load_u8 v0, v0, s[0:3], s4 offen
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; GFX12-NEXT: v_mov_b32_e32 v1, 0
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; GFX12-NEXT: s_mov_b32 s8, s5
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; GFX12-NEXT: s_mov_b32 s9, s6
93+
; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: global_store_b32 v1, v0, s[8:9]
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; GFX12-NEXT: s_endpgm
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%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
97+
%zext = zext i8 %val to i32
98+
store i32 %zext, ptr addrspace(1) %out
99+
ret void
100+
}
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define amdgpu_ps void @test_buffer_load_i8_divergent(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_i8_divergent:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
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; GFX12-NEXT: buffer_load_i8 v0, v0, s[0:3], s5 offen
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: global_store_b32 v1, v0, s[6:7]
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; GFX12-NEXT: s_endpgm
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%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
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%sext = sext i8 %val to i32
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store i32 %sext, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_buffer_load_u16_divergent(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
117+
; GFX12-LABEL: test_buffer_load_u16_divergent:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: buffer_load_u16 v0, off, s[0:3], s4
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; GFX12-NEXT: v_mov_b32_e32 v1, 0
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; GFX12-NEXT: s_mov_b32 s8, s5
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; GFX12-NEXT: s_mov_b32 s9, s6
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: global_store_b32 v1, v0, s[8:9]
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; GFX12-NEXT: s_endpgm
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%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
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%zext = zext i16 %val to i32
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store i32 %zext, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_ps void @test_buffer_load_i16_divergent(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
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; GFX12-LABEL: test_buffer_load_i16_divergent:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: buffer_load_i16 v0, v0, s[0:3], null offen
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; GFX12-NEXT: v_mov_b32_e32 v1, 0
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; GFX12-NEXT: s_mov_b32 s4, s5
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; GFX12-NEXT: s_mov_b32 s5, s6
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: global_store_b32 v1, v0, s[4:5]
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; GFX12-NEXT: s_endpgm
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%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
143+
%sext = sext i16 %val to i32
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store i32 %sext, ptr addrspace(1) %out
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ret void
146+
}
147+
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define amdgpu_ps void @test_buffer_load_u8_waterfall_rsrc(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
149+
; GFX12-LABEL: test_buffer_load_u8_waterfall_rsrc:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1
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; GFX12-NEXT: s_mov_b32 s8, s1
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; GFX12-NEXT: s_mov_b32 s9, s2
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; GFX12-NEXT: s_mov_b32 s2, exec_lo
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; GFX12-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
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; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX12-NEXT: v_readfirstlane_b32 s4, v5
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; GFX12-NEXT: s_wait_loadcnt 0x0
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; GFX12-NEXT: v_readfirstlane_b32 s5, v6
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; GFX12-NEXT: v_readfirstlane_b32 s6, v2
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; GFX12-NEXT: v_readfirstlane_b32 s7, v3
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; GFX12-NEXT: s_wait_alu 0xf1ff
163+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
164+
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[5:6]
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; GFX12-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
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; GFX12-NEXT: s_and_b32 s1, vcc_lo, s1
167+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: s_and_saveexec_b32 s1, s1
169+
; GFX12-NEXT: buffer_load_u8 v6, v4, s[4:7], s0 offen
170+
; GFX12-NEXT: ; implicit-def: $vgpr5
171+
; GFX12-NEXT: ; implicit-def: $vgpr4
172+
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
173+
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s1
174+
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
175+
; GFX12-NEXT: ; %bb.2:
176+
; GFX12-NEXT: s_mov_b32 exec_lo, s2
177+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
178+
; GFX12-NEXT: s_wait_loadcnt 0x0
179+
; GFX12-NEXT: global_store_b32 v0, v6, s[8:9]
180+
; GFX12-NEXT: s_endpgm
181+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
182+
%zext = zext i8 %val to i32
183+
store i32 %zext, ptr addrspace(1) %out
184+
ret void
185+
}
186+
187+
define amdgpu_ps void @test_buffer_load_i8_waterfall_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 %soffset, ptr addrspace(1) inreg %out) {
188+
; GFX12-LABEL: test_buffer_load_i8_waterfall_soffset:
189+
; GFX12: ; %bb.0:
190+
; GFX12-NEXT: s_mov_b32 s6, exec_lo
191+
; GFX12-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
192+
; GFX12-NEXT: v_readfirstlane_b32 s8, v1
193+
; GFX12-NEXT: s_mov_b32 s7, exec_lo
194+
; GFX12-NEXT: s_wait_alu 0xf1ff
195+
; GFX12-NEXT: v_cmpx_eq_u32_e64 s8, v1
196+
; GFX12-NEXT: s_wait_loadcnt 0x0
197+
; GFX12-NEXT: buffer_load_i8 v2, v0, s[0:3], s8 offen
198+
; GFX12-NEXT: ; implicit-def: $vgpr1
199+
; GFX12-NEXT: ; implicit-def: $vgpr0
200+
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s7
201+
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
202+
; GFX12-NEXT: ; %bb.2:
203+
; GFX12-NEXT: s_mov_b32 exec_lo, s6
204+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
205+
; GFX12-NEXT: s_wait_loadcnt 0x0
206+
; GFX12-NEXT: global_store_b32 v0, v2, s[4:5]
207+
; GFX12-NEXT: s_endpgm
208+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
209+
%sext = sext i8 %val to i32
210+
store i32 %sext, ptr addrspace(1) %out
211+
ret void
212+
}
213+
214+
define amdgpu_ps void @test_buffer_load_u16_waterfall_both(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, ptr addrspace(1) inreg %out) {
215+
; GFX12-LABEL: test_buffer_load_u16_waterfall_both:
216+
; GFX12: ; %bb.0:
217+
; GFX12-NEXT: v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v7, v1
218+
; GFX12-NEXT: s_mov_b32 s8, exec_lo
219+
; GFX12-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1
220+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
221+
; GFX12-NEXT: v_readfirstlane_b32 s4, v6
222+
; GFX12-NEXT: s_wait_loadcnt 0x0
223+
; GFX12-NEXT: v_readfirstlane_b32 s5, v7
224+
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
225+
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
226+
; GFX12-NEXT: v_readfirstlane_b32 s9, v5
227+
; GFX12-NEXT: s_wait_alu 0xf1ff
228+
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[6:7]
229+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
230+
; GFX12-NEXT: v_cmp_eq_u64_e64 s2, s[6:7], v[2:3]
231+
; GFX12-NEXT: v_cmp_eq_u32_e64 s3, s9, v5
232+
; GFX12-NEXT: s_and_b32 s2, vcc_lo, s2
233+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
234+
; GFX12-NEXT: s_and_b32 s2, s2, s3
235+
; GFX12-NEXT: s_and_saveexec_b32 s2, s2
236+
; GFX12-NEXT: buffer_load_u16 v7, v4, s[4:7], s9 offen
237+
; GFX12-NEXT: ; implicit-def: $vgpr6
238+
; GFX12-NEXT: ; implicit-def: $vgpr5
239+
; GFX12-NEXT: ; implicit-def: $vgpr4
240+
; GFX12-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3
241+
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s2
242+
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
243+
; GFX12-NEXT: ; %bb.2:
244+
; GFX12-NEXT: s_mov_b32 exec_lo, s8
245+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
246+
; GFX12-NEXT: s_wait_loadcnt 0x0
247+
; GFX12-NEXT: global_store_b32 v0, v7, s[0:1]
248+
; GFX12-NEXT: s_endpgm
249+
%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
250+
%zext = zext i16 %val to i32
251+
store i32 %zext, ptr addrspace(1) %out
252+
ret void
253+
}
254+
255+
declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32 immarg) #0
256+
declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32 immarg) #0
257+
attributes #0 = { nounwind readonly willreturn }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX8 %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX8 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
55
; FIXME: Test with SI when argument lowering not broken for f16
66

77
; Natural mapping

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
33
; FIXME: Test with SI when argument lowering not broken for f16
44

55
; Natural mapping

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s
55

66
; Natural mapping
77
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
33

44
; Natural mapping
55
define amdgpu_ps float @struct_ptr_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

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