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[DAGCombiner] Include custom umin 
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2 files changed

+17
-21
lines changed

2 files changed

+17
-21
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -859,7 +859,7 @@ namespace {
859859
auto LK = TLI.getTypeConversion(*DAG.getContext(), VT);
860860
return (LK.first == TargetLoweringBase::TypeLegal ||
861861
LK.first == TargetLoweringBase::TypePromoteInteger) &&
862-
TLI.isOperationLegal(ISD::UMIN, LK.second);
862+
TLI.isOperationLegalOrCustom(ISD::UMIN, LK.second);
863863
}
864864

865865
public:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll‎

Lines changed: 16 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -5712,9 +5712,8 @@ define <8 x i8> @vsub_if_uge_v8i8(<8 x i8> %va, <8 x i8> %vb) {
57125712
; CHECK-LABEL: vsub_if_uge_v8i8:
57135713
; CHECK: # %bb.0:
57145714
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
5715-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57165715
; CHECK-NEXT: vsub.vv v9, v8, v9
5717-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5716+
; CHECK-NEXT: vminu.vv v8, v8, v9
57185717
; CHECK-NEXT: ret
57195718
%cmp = icmp ult <8 x i8> %va, %vb
57205719
%select = select <8 x i1> %cmp, <8 x i8> zeroinitializer, <8 x i8> %vb
@@ -5725,9 +5724,9 @@ define <8 x i8> @vsub_if_uge_v8i8(<8 x i8> %va, <8 x i8> %vb) {
57255724
define <8 x i8> @vsub_if_uge_swapped_v8i8(<8 x i8> %va, <8 x i8> %vb) {
57265725
; CHECK-LABEL: vsub_if_uge_swapped_v8i8:
57275726
; CHECK: # %bb.0:
5728-
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
5729-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5730-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5727+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
5728+
; CHECK-NEXT: vsub.vv v9, v8, v9
5729+
; CHECK-NEXT: vminu.vv v8, v8, v9
57315730
; CHECK-NEXT: ret
57325731
%cmp = icmp uge <8 x i8> %va, %vb
57335732
%select = select <8 x i1> %cmp, <8 x i8> %vb, <8 x i8> zeroinitializer
@@ -5739,9 +5738,8 @@ define <8 x i16> @vsub_if_uge_v8i16(<8 x i16> %va, <8 x i16> %vb) {
57395738
; CHECK-LABEL: vsub_if_uge_v8i16:
57405739
; CHECK: # %bb.0:
57415740
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5742-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57435741
; CHECK-NEXT: vsub.vv v9, v8, v9
5744-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5742+
; CHECK-NEXT: vminu.vv v8, v8, v9
57455743
; CHECK-NEXT: ret
57465744
%cmp = icmp ult <8 x i16> %va, %vb
57475745
%select = select <8 x i1> %cmp, <8 x i16> zeroinitializer, <8 x i16> %vb
@@ -5752,9 +5750,9 @@ define <8 x i16> @vsub_if_uge_v8i16(<8 x i16> %va, <8 x i16> %vb) {
57525750
define <8 x i16> @vsub_if_uge_swapped_v8i16(<8 x i16> %va, <8 x i16> %vb) {
57535751
; CHECK-LABEL: vsub_if_uge_swapped_v8i16:
57545752
; CHECK: # %bb.0:
5755-
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
5756-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5757-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5753+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
5754+
; CHECK-NEXT: vsub.vv v9, v8, v9
5755+
; CHECK-NEXT: vminu.vv v8, v8, v9
57585756
; CHECK-NEXT: ret
57595757
%cmp = icmp uge <8 x i16> %va, %vb
57605758
%select = select <8 x i1> %cmp, <8 x i16> %vb, <8 x i16> zeroinitializer
@@ -5766,9 +5764,8 @@ define <4 x i32> @vsub_if_uge_v4i32(<4 x i32> %va, <4 x i32> %vb) {
57665764
; CHECK-LABEL: vsub_if_uge_v4i32:
57675765
; CHECK: # %bb.0:
57685766
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5769-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57705767
; CHECK-NEXT: vsub.vv v9, v8, v9
5771-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5768+
; CHECK-NEXT: vminu.vv v8, v8, v9
57725769
; CHECK-NEXT: ret
57735770
%cmp = icmp ult <4 x i32> %va, %vb
57745771
%select = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %vb
@@ -5779,9 +5776,9 @@ define <4 x i32> @vsub_if_uge_v4i32(<4 x i32> %va, <4 x i32> %vb) {
57795776
define <4 x i32> @vsub_if_uge_swapped_v4i32(<4 x i32> %va, <4 x i32> %vb) {
57805777
; CHECK-LABEL: vsub_if_uge_swapped_v4i32:
57815778
; CHECK: # %bb.0:
5782-
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
5783-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5784-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5779+
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
5780+
; CHECK-NEXT: vsub.vv v9, v8, v9
5781+
; CHECK-NEXT: vminu.vv v8, v8, v9
57855782
; CHECK-NEXT: ret
57865783
%cmp = icmp uge <4 x i32> %va, %vb
57875784
%select = select <4 x i1> %cmp, <4 x i32> %vb, <4 x i32> zeroinitializer
@@ -5793,9 +5790,8 @@ define <2 x i64> @vsub_if_uge_v2i64(<2 x i64> %va, <2 x i64> %vb) {
57935790
; CHECK-LABEL: vsub_if_uge_v2i64:
57945791
; CHECK: # %bb.0:
57955792
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5796-
; CHECK-NEXT: vmsltu.vv v0, v8, v9
57975793
; CHECK-NEXT: vsub.vv v9, v8, v9
5798-
; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
5794+
; CHECK-NEXT: vminu.vv v8, v8, v9
57995795
; CHECK-NEXT: ret
58005796
%cmp = icmp ult <2 x i64> %va, %vb
58015797
%select = select <2 x i1> %cmp, <2 x i64> zeroinitializer, <2 x i64> %vb
@@ -5806,9 +5802,9 @@ define <2 x i64> @vsub_if_uge_v2i64(<2 x i64> %va, <2 x i64> %vb) {
58065802
define <2 x i64> @vsub_if_uge_swapped_v2i64(<2 x i64> %va, <2 x i64> %vb) {
58075803
; CHECK-LABEL: vsub_if_uge_swapped_v2i64:
58085804
; CHECK: # %bb.0:
5809-
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
5810-
; CHECK-NEXT: vmsleu.vv v0, v9, v8
5811-
; CHECK-NEXT: vsub.vv v8, v8, v9, v0.t
5805+
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
5806+
; CHECK-NEXT: vsub.vv v9, v8, v9
5807+
; CHECK-NEXT: vminu.vv v8, v8, v9
58125808
; CHECK-NEXT: ret
58135809
%cmp = icmp uge <2 x i64> %va, %vb
58145810
%select = select <2 x i1> %cmp, <2 x i64> %vb, <2 x i64> zeroinitializer

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