[AArch64] Shifted defination OPERAND_MSL_SHIFT for readability NFC

Author: lakshayk-nv

llvm/lib/Target/AArch64/AArch64InstrFormats.td

@@ -1238,6 +1238,17 @@ def timm32_0_255 : Operand<i32>, TImmLeaf<i32, [{
 
 } // let OperandType = "OPERAND_IMMEDIATE"
 
+let OperandType = "OPERAND_MSL_SHIFT" in {
+  // A vector move shifter operand:
+  //  {0} - imm1: #8 or #16
+  def move_vec_shift : Operand<i32> {
+    let PrintMethod = "printShifter";
+    let OperandNamespace = "AArch64";
+    let EncoderMethod = "getMoveVecShifterOpValue";
+    let ParserMatchClass = MoveVecShifterOperand;
+  }
+} // let OperandType = "OPERAND_MSL_SHIFT"
+
 // An arithmetic shifter operand:
 //  {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
 //  {5-0} - imm6
@@ -1316,16 +1327,6 @@ def logical_vec_hw_shift : Operand<i32> {
   let ParserMatchClass = LogicalVecHalfWordShifterOperand;
 }
 
-// A vector move shifter operand:
-//  {0} - imm1: #8 or #16
-def move_vec_shift : Operand<i32> {
-  let OperandNamespace = "AArch64";
-  let PrintMethod = "printShifter";
-  let OperandType = "OPERAND_MSL_SHIFT";
-  let EncoderMethod = "getMoveVecShifterOpValue";
-  let ParserMatchClass = MoveVecShifterOperand;
-}
-
 let DiagnosticType = "AddSubSecondSource" in {
   def AddSubImmOperand : AsmOperandClass {
     let Name = "AddSubImm";
@@ -8893,7 +8894,6 @@ class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
   bits<1> shift;
   let Inst{15-13} = cmode{3-1};
   let Inst{12}    = shift;
-  let Inst{30} = Q;
 }
 
 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bit op2, bits<4> cmode,