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Fix formatting
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llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4928,22 +4928,23 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
49284928
SrcModTrue ? SrcModTrue.getValueType() : SrcModFalse.getValueType();
49294929
SDValue FLHS =
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SrcModTrue ? SrcModTrue : DAG.getNode(ISD::BITCAST, SL, FVT, LHS);
4931-
SDValue FRHS = SrcModFalse ? SrcModFalse
4932-
: DAG.getNode(ISD::BITCAST, SL, FVT, RHS);
4931+
SDValue FRHS =
4932+
SrcModFalse ? SrcModFalse : DAG.getNode(ISD::BITCAST, SL, FVT, RHS);
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SDValue FSelect = DAG.getNode(ISD::SELECT, SL, FVT, Cond, FLHS, FRHS);
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return DAG.getNode(ISD::BITCAST, SL, VT, FSelect);
4935-
}
4936-
return SDValue();
4937-
};
4935+
}
4936+
return SDValue();
4937+
};
49384938

49394939
// Support source modifiers on integer operands.
49404940
if (VT == MVT::i32 || VT == MVT::v2i32)
49414941
if (SDValue F = FoldSrcMods(True, False, VT))
49424942
return F;
49434943

4944-
// For i64 if a source modifier is to be folded in we split into two i32
4945-
// select of high and low values. The Operator need only be applied to the
4946-
// high values in order to change the sign bit.
4944+
// auto SplitSelect = [&]() -> std::pair(
4945+
// For i64 if a source modifier is to be folded in we split into two i32
4946+
// select of high and low values. The Operator need only be applied to the
4947+
// high values in order to change the sign bit.
49474948
if (VT == MVT::i64) {
49484949
bool TrueHasModifierOp =
49494950
(True.getOpcode() == ISD::AND || True.getOpcode() == ISD::OR ||
@@ -5024,7 +5025,7 @@ SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
50245025
return Res;
50255026
}
50265027
}
5027-
}
5028+
}
50285029

50295030
// There's no reason to not do this if the condition has other uses.
50305031
return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);

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