Combine (X ^ Y) and (X == Y) where appropriate

In RISCV, modify the folding of (X ^ Y == 0) -> (X == Y) to account for
cases where the (X ^ Y) will be re-used.

Fixes #130510.

Author: bababuck

llvm/lib/CodeGen/CodeGenPrepare.cpp

@@ -8578,7 +8578,8 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI,
     }
     if (Cmp->isEquality() &&
         (match(UI, m_Add(m_Specific(X), m_SpecificInt(-CmpC))) ||
-         match(UI, m_Sub(m_Specific(X), m_SpecificInt(CmpC))))) {
+         match(UI, m_Sub(m_Specific(X), m_SpecificInt(CmpC))) ||
+         match(UI, m_Xor(m_Specific(X), m_SpecificInt(CmpC))))) {
       IRBuilder<> Builder(Branch);
       if (UI->getParent() != Branch->getParent())
         UI->moveBefore(Branch->getIterator());

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -17194,12 +17194,58 @@ static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
     return true;
   }
 
+  // If XOR is reused and has an immediate that will fit in XORI,
+  // do not fold.
+  auto IsXorImmediate = [](const SDValue &Op) -> bool {
+    if (const auto XorCnst = dyn_cast<ConstantSDNode>(Op))
+      return isInt<12>(XorCnst->getSExtValue());
+    return false;
+  };
+  // Fold (X(i1) ^ 1) == 0 -> X != 0
+  auto SingleBitOp = [&DAG](const SDValue &VarOp,
+                            const SDValue &ConstOp) -> bool {
+    if (const auto XorCnst = dyn_cast<ConstantSDNode>(ConstOp)) {
+      const APInt Mask = APInt::getBitsSetFrom(VarOp.getValueSizeInBits(), 1);
+      return (XorCnst->getSExtValue() == 1) &&
+             DAG.MaskedValueIsZero(VarOp, Mask);
+    }
+    return false;
+  };
+  auto OnlyUsedBySelectOrBR = [](const SDValue &Op) -> bool {
+    for (const SDNode *UserNode : Op->users()) {
+      const unsigned Opcode = UserNode->getOpcode();
+      if (Opcode != RISCVISD::SELECT_CC && Opcode != RISCVISD::BR_CC)
+        return false;
+    }
+    return true;
+  };
+  auto IsFoldableXorEq = [IsXorImmediate, SingleBitOp, OnlyUsedBySelectOrBR](
+                             const SDValue &LHS, const SDValue &RHS) -> bool {
+    return LHS.getOpcode() == ISD::XOR && isNullConstant(RHS) &&
+           (!IsXorImmediate(LHS.getOperand(1)) ||
+            SingleBitOp(LHS.getOperand(0), LHS.getOperand(1)) ||
+            OnlyUsedBySelectOrBR(LHS));
+  };
   // Fold ((xor X, Y), 0, eq/ne) -> (X, Y, eq/ne)
-  if (LHS.getOpcode() == ISD::XOR && isNullConstant(RHS)) {
+  if (IsFoldableXorEq(LHS, RHS)) {
     RHS = LHS.getOperand(1);
     LHS = LHS.getOperand(0);
     return true;
   }
+  // Fold ((sext (xor X, C)), 0, eq/ne) -> ((sext(X), C, eq/ne)
+  if (LHS.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    const SDValue LHS0 = LHS.getOperand(0);
+    if (IsFoldableXorEq(LHS0, RHS) && isa<ConstantSDNode>(LHS0.getOperand(1))) {
+      // SEXT(XOR(X, Y)) -> XOR(SEXT(X), SEXT(Y)))
+      RHS = DAG.getNode(
+          ISD::SIGN_EXTEND_INREG, DL, LHS.getValueType(), LHS0.getOperand(1),
+          DAG.getValueType(cast<VTSDNode>(LHS.getOperand(1))->getVT()));
+      LHS = DAG.getNode(
+          ISD::SIGN_EXTEND_INREG, DL, LHS.getValueType(), LHS0.getOperand(0),
+          DAG.getValueType(cast<VTSDNode>(LHS.getOperand(1))->getVT()));
+      return true;
+    }
+  }
 
   // Fold ((srl (and X, 1<<C), C), 0, eq/ne) -> ((shl X, XLen-1-C), 0, ge/lt)
   if (isNullConstant(RHS) && LHS.getOpcode() == ISD::SRL && LHS.hasOneUse() &&

llvm/test/CodeGen/RISCV/select-constant-xor.ll

@@ -243,10 +243,9 @@ define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
 define i32 @xor_branch_imm_ret(i32 %x) {
 ; RV32-LABEL: xor_branch_imm_ret:
 ; RV32:       # %bb.0: # %entry
-; RV32-NEXT:    li a1, -1365
-; RV32-NEXT:    beq a0, a1, .LBB11_2
-; RV32-NEXT:  # %bb.1: # %if.then
 ; RV32-NEXT:    xori a0, a0, -1365
+; RV32-NEXT:    beqz a0, .LBB11_2
+; RV32-NEXT:  # %bb.1: # %if.then
 ; RV32-NEXT:    ret
 ; RV32-NEXT:  .LBB11_2: # %if.end
 ; RV32-NEXT:    addi sp, sp, -16
@@ -257,11 +256,10 @@ define i32 @xor_branch_imm_ret(i32 %x) {
 ;
 ; RV64-LABEL: xor_branch_imm_ret:
 ; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    xori a0, a0, -1365
 ; RV64-NEXT:    sext.w a1, a0
-; RV64-NEXT:    li a2, -1365
-; RV64-NEXT:    beq a1, a2, .LBB11_2
+; RV64-NEXT:    beqz a1, .LBB11_2
 ; RV64-NEXT:  # %bb.1: # %if.then
-; RV64-NEXT:    xori a0, a0, -1365
 ; RV64-NEXT:    ret
 ; RV64-NEXT:  .LBB11_2: # %if.end
 ; RV64-NEXT:    addi sp, sp, -16
@@ -298,9 +296,9 @@ define i32 @xor_branch_ret(i32 %x) {
 ;
 ; RV64-LABEL: xor_branch_ret:
 ; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    sext.w a2, a0
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:    slli a1, a1, 11
+; RV64-NEXT:    sext.w a2, a0
 ; RV64-NEXT:    beq a2, a1, .LBB12_2
 ; RV64-NEXT:  # %bb.1: # %if.then
 ; RV64-NEXT:    xor a0, a0, a1