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[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16
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6 files changed

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-138
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6 files changed

+690
-138
lines changed

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 32 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -363,6 +363,21 @@ static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
363363
(AMDGPU::OperandSemantics)OperandSemantics));
364364
}
365365

366+
static DecodeStatus decodeOperand_VGPR_16(MCInst &Inst, unsigned Imm,
367+
uint64_t /*Addr*/,
368+
const MCDisassembler *Decoder) {
369+
assert(isUInt<10>(Imm) && "10-bit encoding expected");
370+
371+
const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
372+
if (Imm & AMDGPU::EncValues::IS_VGPR) {
373+
bool IsHi = Imm & (1 << 9);
374+
unsigned RegIdx = Imm & 0xff;
375+
return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
376+
}
377+
return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16,
378+
Imm & 0xFF, false, 0));
379+
}
380+
366381
static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,
367382
uint64_t Addr,
368383
const MCDisassembler *Decoder) {
@@ -763,14 +778,23 @@ void AMDGPUDisassembler::convertEXPInst(MCInst &MI) const {
763778
}
764779

765780
void AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const {
766-
if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 ||
767-
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 ||
768-
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 ||
769-
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 ||
770-
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 ||
771-
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 ||
772-
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 ||
773-
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) {
781+
convertTrue16OpSel(MI);
782+
if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx11 ||
783+
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx11 ||
784+
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_t16_gfx12 ||
785+
MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_fake16_gfx12 ||
786+
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx11 ||
787+
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx11 ||
788+
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_t16_gfx12 ||
789+
MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_fake16_gfx12 ||
790+
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx11 ||
791+
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx11 ||
792+
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_t16_gfx12 ||
793+
MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_fake16_gfx12 ||
794+
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx11 ||
795+
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx11 ||
796+
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_t16_gfx12 ||
797+
MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_fake16_gfx12) {
774798
// The MCInst has this field that is not directly encoded in the
775799
// instruction.
776800
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel);

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1244,6 +1244,14 @@ def VRegSrc_128: SrcReg9<VReg_128, "OPW128">;
12441244
def VRegSrc_256: SrcReg9<VReg_256, "OPW256">;
12451245
def VRegOrLdsSrc_32 : SrcReg9<VRegOrLds_32, "OPW32">;
12461246

1247+
// True 16 Operands
1248+
def VRegSrc_16 : RegisterOperand<VGPR_16> {
1249+
let DecoderMethod = "decodeOperand_VGPR_16";
1250+
let EncoderMethod = "getMachineOpValueT16";
1251+
}
1252+
def VRegSrc_fake16: SrcReg9<VGPR_32, "OPW16"> {
1253+
let EncoderMethod = "getMachineOpValueT16";
1254+
}
12471255
//===----------------------------------------------------------------------===//
12481256
// VGPRSrc_*
12491257
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/VINTERPInstructions.td‎

Lines changed: 90 additions & 58 deletions
Original file line numberDiff line numberDiff line change
@@ -11,29 +11,30 @@
1111
//===----------------------------------------------------------------------===//
1212

1313
class VINTERPe <VOPProfile P> : Enc64 {
14-
bits<8> vdst;
14+
bits<11> vdst;
1515
bits<4> src0_modifiers;
16-
bits<9> src0;
16+
bits<11> src0;
1717
bits<3> src1_modifiers;
18-
bits<9> src1;
18+
bits<11> src1;
1919
bits<3> src2_modifiers;
20-
bits<9> src2;
20+
bits<11> src2;
2121
bits<1> clamp;
2222
bits<3> waitexp;
2323

2424
let Inst{31-26} = 0x33; // VOP3P encoding
2525
let Inst{25-24} = 0x1; // VINTERP sub-encoding
2626

27-
let Inst{7-0} = vdst;
27+
let Inst{7-0} = vdst{7-0};
2828
let Inst{10-8} = waitexp;
29-
let Inst{11} = !if(P.HasOpSel, src0_modifiers{2}, 0); // op_sel(0)
30-
let Inst{12} = !if(P.HasOpSel, src1_modifiers{2}, 0); // op_sel(1)
31-
let Inst{13} = !if(P.HasOpSel, src2_modifiers{2}, 0); // op_sel(2)
32-
let Inst{14} = !if(P.HasOpSel, src0_modifiers{3}, 0); // op_sel(3)
29+
// Fields for hi/lo 16-bits of register selection
30+
let Inst{11} = !if(P.HasSrc0, src0_modifiers{2}, 0);
31+
let Inst{12} = !if(P.HasSrc1, src1_modifiers{2}, 0);
32+
let Inst{13} = !if(P.HasSrc2, src2_modifiers{2}, 0);
33+
let Inst{14} = !if(P.HasDst, src0_modifiers{3}, 0);
3334
let Inst{15} = clamp;
34-
let Inst{40-32} = src0;
35-
let Inst{49-41} = src1;
36-
let Inst{58-50} = src2;
35+
let Inst{40-32} = src0{8-0};
36+
let Inst{49-41} = src1{8-0};
37+
let Inst{58-50} = src2{8-0};
3738
let Inst{61} = src0_modifiers{0}; // neg(0)
3839
let Inst{62} = src1_modifiers{0}; // neg(1)
3940
let Inst{63} = src2_modifiers{0}; // neg(2)
@@ -60,9 +61,10 @@ class VINTERP_Pseudo <string OpName, VOPProfile P, list<dag> pattern = []> :
6061
let VINTERP = 1;
6162
}
6263

63-
class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily> :
64-
VOP3_Real <ps, EncodingFamily> {
64+
class VINTERP_Real <VOP_Pseudo ps, int EncodingFamily, string asmName> :
65+
VOP3_Real <ps, EncodingFamily, asmName> {
6566
let VINTERP = 1;
67+
let IsSingle = 1;
6668
}
6769

6870
def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
@@ -83,44 +85,64 @@ def VOP3_VINTERP_F32 : VOPProfile<[f32, f32, f32, f32]> {
8385
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$waitexp";
8486
}
8587

86-
class VOP3_VINTERP_F16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
87-
let HasOpSel = 1;
88-
let HasModifiers = 1;
88+
class VOP3_VINTERP_F16_t16 <list<ValueType> ArgVT> : VOPProfile_True16<VOPProfile<ArgVT>> {
89+
let Src0Mod = FPT16VRegInputMods</*Fake16*/0>;
90+
let Src1Mod = FPVRegInputMods;
91+
let Src2Mod = !if(!eq(ArgVT[3].Size, 16), FPT16VRegInputMods</*Fake16*/0>,
92+
FPVRegInputMods);
93+
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_16:$src0,
94+
Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
95+
Src2Mod:$src2_modifiers,
96+
!if(!eq(ArgVT[3].Size, 16), VRegSrc_16, VRegSrc_32):$src2,
97+
Clamp:$clamp, op_sel0:$op_sel,
98+
WaitEXP:$waitexp);
8999

90-
let Src0Mod = FPVRegInputMods;
100+
let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
101+
}
102+
103+
class VOP3_VINTERP_F16_fake16 <list<ValueType> ArgVT> : VOPProfile_Fake16<VOPProfile<ArgVT>> {
104+
let Src0Mod = FPT16VRegInputMods</*Fake16*/1>;
91105
let Src1Mod = FPVRegInputMods;
92-
let Src2Mod = FPVRegInputMods;
106+
let Src2Mod = !if(!eq(ArgVT[3].Size, 16), FPT16VRegInputMods</*Fake16*/1>,
107+
FPVRegInputMods);
93108

94-
let Outs64 = (outs VGPR_32:$vdst);
95-
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
109+
let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_fake16:$src0,
96110
Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
97-
Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
111+
Src2Mod:$src2_modifiers,
112+
!if(!eq(ArgVT[3].Size, 16), VRegSrc_fake16, VRegSrc_32):$src2,
98113
Clamp:$clamp, op_sel0:$op_sel,
99114
WaitEXP:$waitexp);
100115

101-
let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
102-
}
116+
let Asm64 = "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$op_sel$waitexp";
117+
}
118+
119+
103120

104121
//===----------------------------------------------------------------------===//
105122
// VINTERP Pseudo Instructions
106123
//===----------------------------------------------------------------------===//
107-
108124
let SubtargetPredicate = HasVINTERPEncoding in {
109125

126+
multiclass VINTERP_t16<string OpName, list<ValueType> ArgVT> {
127+
let True16Predicate = UseRealTrue16Insts in {
128+
def _t16 : VINTERP_Pseudo<OpName#"_t16", VOP3_VINTERP_F16_t16<ArgVT>> ;
129+
}
130+
let True16Predicate = UseFakeTrue16Insts in {
131+
def _fake16 : VINTERP_Pseudo<OpName#"_fake16", VOP3_VINTERP_F16_fake16<ArgVT>> ;
132+
}
133+
}
134+
110135
let Uses = [M0, EXEC, MODE] in {
111136
def V_INTERP_P10_F32_inreg : VINTERP_Pseudo <"v_interp_p10_f32", VOP3_VINTERP_F32>;
112137
def V_INTERP_P2_F32_inreg : VINTERP_Pseudo <"v_interp_p2_f32", VOP3_VINTERP_F32>;
113-
def V_INTERP_P10_F16_F32_inreg :
114-
VINTERP_Pseudo <"v_interp_p10_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
115-
def V_INTERP_P2_F16_F32_inreg :
116-
VINTERP_Pseudo <"v_interp_p2_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
138+
139+
defm V_INTERP_P10_F16_F32_inreg : VINTERP_t16<"v_interp_p10_f16_f32", [f32, f16, f32, f16]>;
140+
defm V_INTERP_P2_F16_F32_inreg : VINTERP_t16<"v_interp_p2_f16_f32", [f16, f16, f32, f32]>;
117141
} // Uses = [M0, EXEC, MODE]
118142

119143
let Uses = [M0, EXEC] in {
120-
def V_INTERP_P10_RTZ_F16_F32_inreg :
121-
VINTERP_Pseudo <"v_interp_p10_rtz_f16_f32", VOP3_VINTERP_F16<[f32, f32, f32, f32]>>;
122-
def V_INTERP_P2_RTZ_F16_F32_inreg :
123-
VINTERP_Pseudo <"v_interp_p2_rtz_f16_f32", VOP3_VINTERP_F16<[f16, f32, f32, f32]>>;
144+
defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_t16<"v_interp_p10_rtz_f16_f32", [f32, f16, f32, f16]>;
145+
defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_t16 <"v_interp_p2_rtz_f16_f32", [f16, f16, f32, f32]>;
124146
} // Uses = [M0, EXEC]
125147

126148
} // SubtargetPredicate = HasVINTERPEncoding.
@@ -137,11 +159,6 @@ class VInterpF32Pat <SDPatternOperator op, Instruction inst> : GCNPat <
137159
7) /* wait_exp */
138160
>;
139161

140-
def VINTERP_OPSEL {
141-
int LOW = 0;
142-
int HIGH = 0xa;
143-
}
144-
145162
class VInterpF16Pat <SDPatternOperator op, Instruction inst,
146163
ValueType dst_type, bit high,
147164
list<ComplexPattern> pat> : GCNPat <
@@ -167,45 +184,60 @@ multiclass VInterpF16Pat <SDPatternOperator op, Instruction inst,
167184

168185
def : VInterpF32Pat<int_amdgcn_interp_inreg_p10, V_INTERP_P10_F32_inreg>;
169186
def : VInterpF32Pat<int_amdgcn_interp_inreg_p2, V_INTERP_P2_F32_inreg>;
187+
188+
let True16Predicate = UseFakeTrue16Insts in {
170189
defm : VInterpF16Pat<int_amdgcn_interp_inreg_p10_f16,
171-
V_INTERP_P10_F16_F32_inreg, f32,
190+
V_INTERP_P10_F16_F32_inreg_fake16, f32,
172191
[VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
173192
defm : VInterpF16Pat<int_amdgcn_interp_inreg_p2_f16,
174-
V_INTERP_P2_F16_F32_inreg, f16,
193+
V_INTERP_P2_F16_F32_inreg_fake16, f16,
175194
[VINTERPModsHi, VINTERPMods, VINTERPMods]>;
176195
defm : VInterpF16Pat<int_amdgcn_interp_p10_rtz_f16,
177-
V_INTERP_P10_RTZ_F16_F32_inreg, f32,
196+
V_INTERP_P10_RTZ_F16_F32_inreg_fake16, f32,
178197
[VINTERPModsHi, VINTERPMods, VINTERPModsHi]>;
179198
defm : VInterpF16Pat<int_amdgcn_interp_p2_rtz_f16,
180-
V_INTERP_P2_RTZ_F16_F32_inreg, f16,
199+
V_INTERP_P2_RTZ_F16_F32_inreg_fake16, f16,
181200
[VINTERPModsHi, VINTERPMods, VINTERPMods]>;
201+
}
182202

183203
//===----------------------------------------------------------------------===//
184204
// VINTERP Real Instructions
185205
//===----------------------------------------------------------------------===//
186206

187-
multiclass VINTERP_Real_gfx11 <bits<7> op> {
188-
let AssemblerPredicate = isGFX11Only, DecoderNamespace = "GFX11" in {
189-
def _gfx11 :
190-
VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
191-
VINTERPe_gfx11<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
207+
multiclass VINTERP_Real_gfx11 <bits<7> op, string asmName> {
208+
defvar ps = !cast<VOP3_Pseudo>(NAME);
209+
let AssemblerPredicate = isGFX11Only,
210+
DecoderNamespace = "GFX11" #
211+
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
212+
def _gfx11 :
213+
VINTERP_Real<ps, SIEncodingFamily.GFX11, asmName>,
214+
VINTERPe_gfx11<op, ps.Pfl>;
192215
}
193216
}
194217

195-
multiclass VINTERP_Real_gfx12 <bits<7> op> {
196-
let AssemblerPredicate = isGFX12Only, DecoderNamespace = "GFX12" in {
197-
def _gfx12 :
198-
VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX12>,
199-
VINTERPe_gfx12<op, !cast<VOP3_Pseudo>(NAME).Pfl>;
218+
multiclass VINTERP_Real_gfx12 <bits<7> op, string asmName> {
219+
defvar ps = !cast<VOP3_Pseudo>(NAME);
220+
let AssemblerPredicate = isGFX12Only,
221+
DecoderNamespace = "GFX12" #
222+
!if(ps.Pfl.IsRealTrue16, "", "_FAKE16") in {
223+
def _gfx12 :
224+
VINTERP_Real<ps, SIEncodingFamily.GFX12, asmName>,
225+
VINTERPe_gfx12<op, ps.Pfl>;
200226
}
201227
}
202228

203-
multiclass VINTERP_Real_gfx11_gfx12 <bits<7> op> :
204-
VINTERP_Real_gfx11<op>, VINTERP_Real_gfx12<op>;
229+
multiclass VINTERP_Real_gfx11_gfx12 <bits<7> op, string asmName = !cast<VOP3_Pseudo>(NAME).Mnemonic, string opName = NAME> :
230+
VINTERP_Real_gfx11<op, asmName>, VINTERP_Real_gfx12<op, asmName>;
231+
232+
multiclass VINTERP_Real_t16_and_fake16_gfx11_gfx12 <bits<7> op, string asmName = !cast<VOP3_Pseudo>(NAME).Mnemonic, string opName = NAME> {
233+
defm _t16: VINTERP_Real_gfx11_gfx12<op, asmName, opName#"_t16">;
234+
defm _fake16: VINTERP_Real_gfx11_gfx12<op, asmName, opName#"_fake16">;
235+
}
236+
205237

206238
defm V_INTERP_P10_F32_inreg : VINTERP_Real_gfx11_gfx12<0x000>;
207239
defm V_INTERP_P2_F32_inreg : VINTERP_Real_gfx11_gfx12<0x001>;
208-
defm V_INTERP_P10_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x002>;
209-
defm V_INTERP_P2_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x003>;
210-
defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x004>;
211-
defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_Real_gfx11_gfx12<0x005>;
240+
defm V_INTERP_P10_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x002, "v_interp_p10_f16_f32">;
241+
defm V_INTERP_P2_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x003, "v_interp_p2_f16_f32">;
242+
defm V_INTERP_P10_RTZ_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x004, "v_interp_p10_rtz_f16_f32">;
243+
defm V_INTERP_P2_RTZ_F16_F32_inreg : VINTERP_Real_t16_and_fake16_gfx11_gfx12<0x005, "v_interp_p2_rtz_f16_f32">;

‎llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -15,16 +15,16 @@ body: |
1515
; GFX11-NEXT: $vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec
1616
; GFX11-NEXT: $vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec
1717
; GFX11-NEXT: $vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec
18-
; GFX11-NEXT: $vgpr5 = V_INTERP_P10_F16_F32_inreg 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
19-
; GFX11-NEXT: $vgpr6 = V_INTERP_P10_F16_F32_inreg 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
20-
; GFX11-NEXT: $vgpr7 = V_INTERP_P10_F16_F32_inreg 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 1, implicit $m0, implicit $exec, implicit $mode
21-
; GFX11-NEXT: $vgpr8 = V_INTERP_P10_F16_F32_inreg 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, implicit $m0, implicit $exec, implicit $mode
18+
; GFX11-NEXT: $vgpr5 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
19+
; GFX11-NEXT: $vgpr6 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
20+
; GFX11-NEXT: $vgpr7 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 1, implicit $m0, implicit $exec, implicit $mode
21+
; GFX11-NEXT: $vgpr8 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 0, implicit $m0, implicit $exec, implicit $mode
2222
$vgpr1 = LDS_PARAM_LOAD 0, 0, 0, implicit $m0, implicit $exec
2323
$vgpr2 = LDS_PARAM_LOAD 0, 1, 0, implicit $m0, implicit $exec
2424
$vgpr3 = LDS_PARAM_LOAD 0, 2, 0, implicit $m0, implicit $exec
2525
$vgpr4 = LDS_PARAM_LOAD 0, 3, 0, implicit $m0, implicit $exec
26-
$vgpr5 = V_INTERP_P10_F16_F32_inreg 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
27-
$vgpr6 = V_INTERP_P10_F16_F32_inreg 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
28-
$vgpr7 = V_INTERP_P10_F16_F32_inreg 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
29-
$vgpr8 = V_INTERP_P10_F16_F32_inreg 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
26+
$vgpr5 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr1, 0, $vgpr0, 0, $vgpr1, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
27+
$vgpr6 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr2, 0, $vgpr0, 0, $vgpr2, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
28+
$vgpr7 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr3, 0, $vgpr0, 0, $vgpr3, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
29+
$vgpr8 = V_INTERP_P10_F16_F32_inreg_fake16 0, $vgpr4, 0, $vgpr0, 0, $vgpr4, 0, 0, 2, implicit $m0, implicit $exec, implicit $mode
3030
...

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