Skip to content

Commit be3a7a6

Browse files
paulwalker-armpaulwalker-arm
authored
[NFC][Clang][AArch64] Simplify ACLE guards within arm_sve.td & arm_sme.td. (#152547)
Only set a target guard if it deviates from its default value[1]. When a target guard is set, it is automatically AND'd with its default value. This means there is no need to use SVETargetGuard="sve,bf16" because SVETargetGuard="bf16" is sufficient. [1] Defaults: SVETargetGuard="sve", SMETargetGuard="sme"
1 parent 2fcdaba commit be3a7a6

File tree

3 files changed

+125
-149
lines changed

3 files changed

+125
-149
lines changed

‎clang/include/clang/Basic/arm_sme.td‎

Lines changed: 78 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -21,23 +21,21 @@ let SVETargetGuard = InvalidMode in {
2121
// Loads
2222

2323
multiclass ZALoad<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
24-
let SMETargetGuard = "sme" in {
25-
def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimPQ", t,
26-
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
27-
MemEltTyDefault, i_prefix # "_horiz", ch>;
28-
29-
def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimPQl", t,
30-
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
31-
MemEltTyDefault, i_prefix # "_horiz", ch>;
32-
33-
def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimPQ", t,
34-
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
35-
MemEltTyDefault, i_prefix # "_vert", ch>;
36-
37-
def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimPQl", t,
38-
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
39-
MemEltTyDefault, i_prefix # "_vert", ch>;
40-
}
24+
def NAME # _H : MInst<"svld1_hor_" # n_suffix, "vimPQ", t,
25+
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
26+
MemEltTyDefault, i_prefix # "_horiz", ch>;
27+
28+
def NAME # _H_VNUM : MInst<"svld1_hor_vnum_" # n_suffix, "vimPQl", t,
29+
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
30+
MemEltTyDefault, i_prefix # "_horiz", ch>;
31+
32+
def NAME # _V : MInst<"svld1_ver_" # n_suffix, "vimPQ", t,
33+
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
34+
MemEltTyDefault, i_prefix # "_vert", ch>;
35+
36+
def NAME # _V_VNUM : MInst<"svld1_ver_vnum_" # n_suffix, "vimPQl", t,
37+
[IsLoad, IsOverloadNone, IsStreaming, IsInOutZA],
38+
MemEltTyDefault, i_prefix # "_vert", ch>;
4139
}
4240

4341
defm SVLD1_ZA8 : ZALoad<"za8", "c", "aarch64_sme_ld1b", [ImmCheck<0, ImmCheck0_0>]>;
@@ -46,37 +44,33 @@ defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0
4644
defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>]>;
4745
defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>;
4846

49-
let SMETargetGuard = "sme" in {
5047
def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "",
5148
[IsOverloadNone, IsStreamingCompatible, IsInOutZA],
5249
MemEltTyDefault, "aarch64_sme_ldr">;
5350

5451
def SVLDR_ZA : MInst<"svldr_za", "vmQ", "",
5552
[IsOverloadNone, IsStreamingCompatible, IsInOutZA],
5653
MemEltTyDefault, "aarch64_sme_ldr", []>;
57-
}
5854

5955
////////////////////////////////////////////////////////////////////////////////
6056
// Stores
6157

6258
multiclass ZAStore<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
63-
let SMETargetGuard = "sme" in {
64-
def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimP%", t,
65-
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
66-
MemEltTyDefault, i_prefix # "_horiz", ch>;
67-
68-
def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimP%l", t,
69-
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
70-
MemEltTyDefault, i_prefix # "_horiz", ch>;
71-
72-
def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimP%", t,
73-
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
74-
MemEltTyDefault, i_prefix # "_vert", ch>;
75-
76-
def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimP%l", t,
77-
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
78-
MemEltTyDefault, i_prefix # "_vert", ch>;
79-
}
59+
def NAME # _H : MInst<"svst1_hor_" # n_suffix, "vimP%", t,
60+
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
61+
MemEltTyDefault, i_prefix # "_horiz", ch>;
62+
63+
def NAME # _H_VNUM : MInst<"svst1_hor_vnum_" # n_suffix, "vimP%l", t,
64+
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
65+
MemEltTyDefault, i_prefix # "_horiz", ch>;
66+
67+
def NAME # _V : MInst<"svst1_ver_" # n_suffix, "vimP%", t,
68+
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
69+
MemEltTyDefault, i_prefix # "_vert", ch>;
70+
71+
def NAME # _V_VNUM : MInst<"svst1_ver_vnum_" # n_suffix, "vimP%l", t,
72+
[IsStore, IsOverloadNone, IsStreaming, IsInZA],
73+
MemEltTyDefault, i_prefix # "_vert", ch>;
8074
}
8175

8276
defm SVST1_ZA8 : ZAStore<"za8", "c", "aarch64_sme_st1b", [ImmCheck<0, ImmCheck0_0>]>;
@@ -85,29 +79,25 @@ defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck
8579
defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>]>;
8680
defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>;
8781

88-
let SMETargetGuard = "sme" in {
8982
def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "",
9083
[IsOverloadNone, IsStreamingCompatible, IsInZA],
9184
MemEltTyDefault, "aarch64_sme_str">;
9285

9386
def SVSTR_ZA : MInst<"svstr_za", "vm%", "",
9487
[IsOverloadNone, IsStreamingCompatible, IsInZA],
9588
MemEltTyDefault, "aarch64_sme_str", []>;
96-
}
9789

9890
////////////////////////////////////////////////////////////////////////////////
9991
// Read horizontal/vertical ZA slices
10092

10193
multiclass ZARead<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
102-
let SMETargetGuard = "sme" in {
103-
def NAME # _H : SInst<"svread_hor_" # n_suffix # "[_{d}]", "ddPim", t,
104-
MergeOp1, i_prefix # "_horiz",
105-
[IsReadZA, IsStreaming, IsInZA], ch>;
106-
107-
def NAME # _V : SInst<"svread_ver_" # n_suffix # "[_{d}]", "ddPim", t,
108-
MergeOp1, i_prefix # "_vert",
109-
[IsReadZA, IsStreaming, IsInZA], ch>;
110-
}
94+
def NAME # _H : SInst<"svread_hor_" # n_suffix # "[_{d}]", "ddPim", t,
95+
MergeOp1, i_prefix # "_horiz",
96+
[IsReadZA, IsStreaming, IsInZA], ch>;
97+
98+
def NAME # _V : SInst<"svread_ver_" # n_suffix # "[_{d}]", "ddPim", t,
99+
MergeOp1, i_prefix # "_vert",
100+
[IsReadZA, IsStreaming, IsInZA], ch>;
111101
}
112102

113103
defm SVREAD_ZA8 : ZARead<"za8", "cUcm", "aarch64_sme_read", [ImmCheck<2, ImmCheck0_0>]>;
@@ -120,15 +110,13 @@ defm SVREAD_ZA128 : ZARead<"za128", "csilUcUsUiUlmhbfd", "aarch64_sme_readq", [I
120110
// Write horizontal/vertical ZA slices
121111

122112
multiclass ZAWrite<string n_suffix, string t, string i_prefix, list<ImmCheck> ch> {
123-
let SMETargetGuard = "sme" in {
124-
def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimPd", t,
125-
MergeOp1, i_prefix # "_horiz",
126-
[IsWriteZA, IsStreaming, IsInOutZA], ch>;
127-
128-
def NAME # _V : SInst<"svwrite_ver_" # n_suffix # "[_{d}]", "vimPd", t,
129-
MergeOp1, i_prefix # "_vert",
130-
[IsWriteZA, IsStreaming, IsInOutZA], ch>;
131-
}
113+
def NAME # _H : SInst<"svwrite_hor_" # n_suffix # "[_{d}]", "vimPd", t,
114+
MergeOp1, i_prefix # "_horiz",
115+
[IsWriteZA, IsStreaming, IsInOutZA], ch>;
116+
117+
def NAME # _V : SInst<"svwrite_ver_" # n_suffix # "[_{d}]", "vimPd", t,
118+
MergeOp1, i_prefix # "_vert",
119+
[IsWriteZA, IsStreaming, IsInOutZA], ch>;
132120
}
133121

134122
defm SVWRITE_ZA8 : ZAWrite<"za8", "cUcm", "aarch64_sme_write", [ImmCheck<0, ImmCheck0_0>]>;
@@ -140,13 +128,11 @@ defm SVWRITE_ZA128 : ZAWrite<"za128", "csilUcUsUiUlmhbfd", "aarch64_sme_writeq",
140128
////////////////////////////////////////////////////////////////////////////////
141129
// SME - Zero
142130

143-
let SMETargetGuard = "sme" in {
144-
def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero",
145-
[IsOverloadNone, IsStreamingCompatible, IsInOutZA],
146-
[ImmCheck<0, ImmCheck0_255>]>;
147-
def SVZERO_ZA : SInst<"svzero_za", "vv", "", MergeNone, "aarch64_sme_zero",
148-
[IsOverloadNone, IsStreamingCompatible, IsOutZA]>;
149-
}
131+
def SVZERO_MASK_ZA : SInst<"svzero_mask_za", "vi", "", MergeNone, "aarch64_sme_zero",
132+
[IsOverloadNone, IsStreamingCompatible, IsInOutZA],
133+
[ImmCheck<0, ImmCheck0_255>]>;
134+
def SVZERO_ZA : SInst<"svzero_za", "vv", "", MergeNone, "aarch64_sme_zero",
135+
[IsOverloadNone, IsStreamingCompatible, IsOutZA]>;
150136

151137
let SMETargetGuard = "sme2p1" in {
152138
def SVZERO_ZA64_VG1x2 : SInst<"svzero_za64_vg1x2", "vm", "", MergeNone, "aarch64_sme_zero_za64_vg1x2",
@@ -171,11 +157,9 @@ let SMETargetGuard = "sme2p1" in {
171157
// SME - Counting elements in a streaming vector
172158

173159
multiclass ZACount<string n_suffix> {
174-
let SMETargetGuard = "sme" in {
175-
def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
176-
"aarch64_sme_" # n_suffix,
177-
[IsOverloadNone, IsStreamingCompatible]>;
178-
}
160+
def NAME : SInst<"sv" # n_suffix, "nv", "", MergeNone,
161+
"aarch64_sme_" # n_suffix,
162+
[IsOverloadNone, IsStreamingCompatible]>;
179163
}
180164

181165
defm SVCNTSB : ZACount<"cntsb">;
@@ -187,11 +171,9 @@ defm SVCNTSD : ZACount<"cntsd">;
187171
// SME - ADDHA/ADDVA
188172

189173
multiclass ZAAdd<string n_suffix> {
190-
let SMETargetGuard = "sme" in {
191-
def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", MergeOp1,
192-
"aarch64_sme_" # n_suffix, [IsStreaming, IsInOutZA],
193-
[ImmCheck<0, ImmCheck0_3>]>;
194-
}
174+
def NAME # _ZA32: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPd", "iUi", MergeOp1,
175+
"aarch64_sme_" # n_suffix, [IsStreaming, IsInOutZA],
176+
[ImmCheck<0, ImmCheck0_3>]>;
195177

196178
let SMETargetGuard = "sme-i16i64" in {
197179
def NAME # _ZA64: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPd", "lUl", MergeOp1,
@@ -207,13 +189,11 @@ defm SVADDVA : ZAAdd<"addva">;
207189
// SME - SMOPA, SMOPS, UMOPA, UMOPS
208190

209191
multiclass ZAIntOuterProd<string n_suffix1, string n_suffix2> {
210-
let SMETargetGuard = "sme" in {
211-
def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]",
212-
"viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "c",
213-
MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
214-
[IsStreaming, IsInOutZA],
215-
[ImmCheck<0, ImmCheck0_3>]>;
216-
}
192+
def NAME # _ZA32_B: SInst<"sv" # n_suffix2 # "_za32[_{d}]",
193+
"viPPdd", !cond(!eq(n_suffix1, "s") : "", true: "U") # "c",
194+
MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
195+
[IsStreaming, IsInOutZA],
196+
[ImmCheck<0, ImmCheck0_3>]>;
217197

218198
let SMETargetGuard = "sme-i16i64" in {
219199
def NAME # _ZA64_H: SInst<"sv" # n_suffix2 # "_za64[_{d}]",
@@ -233,14 +213,12 @@ defm SVUMOPS : ZAIntOuterProd<"u", "mops">;
233213
// SME - SUMOPA, SUMOPS, USMOPA, USMOPS
234214

235215
multiclass ZAIntOuterProdMixedSigns<string n_suffix1, string n_suffix2> {
236-
let SMETargetGuard = "sme" in {
237-
def NAME # _ZA32_B: SInst<"sv" # n_suffix1 # n_suffix2 # "_za32[_{d}]",
238-
"viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"),
239-
!cond(!eq(n_suffix1, "su") : "", true: "U") # "c",
240-
MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
241-
[IsStreaming, IsInOutZA],
242-
[ImmCheck<0, ImmCheck0_3>]>;
243-
}
216+
def NAME # _ZA32_B: SInst<"sv" # n_suffix1 # n_suffix2 # "_za32[_{d}]",
217+
"viPPd" # !cond(!eq(n_suffix1, "su") : "u", true: "x"),
218+
!cond(!eq(n_suffix1, "su") : "", true: "U") # "c",
219+
MergeOp1, "aarch64_sme_" # n_suffix1 # n_suffix2 # "_wide",
220+
[IsStreaming, IsInOutZA],
221+
[ImmCheck<0, ImmCheck0_3>]>;
244222

245223
let SMETargetGuard = "sme-i16i64" in {
246224
def NAME # _ZA64_H: SInst<"sv" # n_suffix1 # n_suffix2 # "_za64[_{d}]",
@@ -261,22 +239,20 @@ defm SVUSMOPS : ZAIntOuterProdMixedSigns<"us", "mops">;
261239
// SME - FMOPA, FMOPS
262240

263241
multiclass ZAFPOuterProd<string n_suffix> {
264-
let SMETargetGuard = "sme" in {
265-
def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h",
266-
MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
267-
[IsStreaming, IsInOutZA],
268-
[ImmCheck<0, ImmCheck0_3>]>;
242+
def NAME # _ZA32_B: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "h",
243+
MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
244+
[IsStreaming, IsInOutZA],
245+
[ImmCheck<0, ImmCheck0_3>]>;
269246

270-
def NAME # _ZA32_H: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "b",
271-
MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
272-
[IsStreaming, IsInOutZA],
273-
[ImmCheck<0, ImmCheck0_3>]>;
247+
def NAME # _ZA32_H: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "b",
248+
MergeOp1, "aarch64_sme_" # n_suffix # "_wide",
249+
[IsStreaming, IsInOutZA],
250+
[ImmCheck<0, ImmCheck0_3>]>;
274251

275-
def NAME # _ZA32_S: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "f",
276-
MergeOp1, "aarch64_sme_" # n_suffix,
277-
[IsStreaming, IsInOutZA],
278-
[ImmCheck<0, ImmCheck0_3>]>;
279-
}
252+
def NAME # _ZA32_S: SInst<"sv" # n_suffix # "_za32[_{d}]", "viPPdd", "f",
253+
MergeOp1, "aarch64_sme_" # n_suffix,
254+
[IsStreaming, IsInOutZA],
255+
[ImmCheck<0, ImmCheck0_3>]>;
280256

281257
let SMETargetGuard = "sme-f64f64" in {
282258
def NAME # _ZA64_D: SInst<"sv" # n_suffix # "_za64[_{d}]", "viPPdd", "d",

0 commit comments

Comments
 (0)