[MC][CodeGen][Mips] Add CodeView mapping (#120877)

hpoussin · web-flow · commit be68f35bf55b · 2025-01-20T15:00:24.000+08:00
Also add support for new relocation types required by debug information.

Constants have been taken from CodeView Symbolic Debug Information
Specification.
diff --git a/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def b/llvm/include/llvm/DebugInfo/CodeView/CodeViewRegisters.def
@@ -16,7 +16,8 @@
 
 #if !defined(CV_REGISTERS_ALL) && !defined(CV_REGISTERS_X86) &&                \
     !defined(CV_REGISTERS_ARM) &&                                              \
-    !defined(CV_REGISTERS_ARM64)
+    !defined(CV_REGISTERS_ARM64) &&                                            \
+    !defined(CV_REGISTERS_MIPS)
 #error Need include at least one register set.
 #endif
 
@@ -793,3 +794,88 @@ CV_REGISTER(ARM64_H31, 301)
 #pragma pop_macro("ARM64_FPCR")
 
 #endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_ARM64)
+
+#if defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_MIPS)
+
+// MIPS registers
+CV_REGISTER(MIPS_NOREG, 0)
+
+// General purpose integer registers
+
+CV_REGISTER(MIPS_ZERO, 10)
+CV_REGISTER(MIPS_AT, 11)
+CV_REGISTER(MIPS_V0, 12)
+CV_REGISTER(MIPS_V1, 13)
+CV_REGISTER(MIPS_A0, 14)
+CV_REGISTER(MIPS_A1, 15)
+CV_REGISTER(MIPS_A2, 16)
+CV_REGISTER(MIPS_A3, 17)
+CV_REGISTER(MIPS_T0, 18)
+CV_REGISTER(MIPS_T1, 19)
+CV_REGISTER(MIPS_T2, 20)
+CV_REGISTER(MIPS_T3, 21)
+CV_REGISTER(MIPS_T4, 22)
+CV_REGISTER(MIPS_T5, 23)
+CV_REGISTER(MIPS_T6, 24)
+CV_REGISTER(MIPS_T7, 25)
+CV_REGISTER(MIPS_S0, 26)
+CV_REGISTER(MIPS_S1, 27)
+CV_REGISTER(MIPS_S2, 28)
+CV_REGISTER(MIPS_S3, 29)
+CV_REGISTER(MIPS_S4, 30)
+CV_REGISTER(MIPS_S5, 31)
+CV_REGISTER(MIPS_S6, 32)
+CV_REGISTER(MIPS_S7, 33)
+CV_REGISTER(MIPS_T8, 34)
+CV_REGISTER(MIPS_T9, 35)
+CV_REGISTER(MIPS_K0, 36)
+CV_REGISTER(MIPS_K1, 37)
+CV_REGISTER(MIPS_GP, 38)
+CV_REGISTER(MIPS_SP, 39)
+CV_REGISTER(MIPS_S8, 40)
+CV_REGISTER(MIPS_RA, 41)
+CV_REGISTER(MIPS_LO, 42)
+CV_REGISTER(MIPS_HI, 43)
+
+// Status registers
+
+CV_REGISTER(MIPS_Fir, 50)
+CV_REGISTER(MIPS_Psr, 51)
+
+// Floating-point registers
+
+CV_REGISTER(MIPS_F0, 60)
+CV_REGISTER(MIPS_F1, 61)
+CV_REGISTER(MIPS_F2, 62)
+CV_REGISTER(MIPS_F3, 63)
+CV_REGISTER(MIPS_F4, 64)
+CV_REGISTER(MIPS_F5, 65)
+CV_REGISTER(MIPS_F6, 66)
+CV_REGISTER(MIPS_F7, 67)
+CV_REGISTER(MIPS_F8, 68)
+CV_REGISTER(MIPS_F9, 69)
+CV_REGISTER(MIPS_F10, 70)
+CV_REGISTER(MIPS_F11, 71)
+CV_REGISTER(MIPS_F12, 72)
+CV_REGISTER(MIPS_F13, 73)
+CV_REGISTER(MIPS_F14, 74)
+CV_REGISTER(MIPS_F15, 75)
+CV_REGISTER(MIPS_F16, 76)
+CV_REGISTER(MIPS_F17, 77)
+CV_REGISTER(MIPS_F18, 78)
+CV_REGISTER(MIPS_F19, 79)
+CV_REGISTER(MIPS_F20, 80)
+CV_REGISTER(MIPS_F21, 81)
+CV_REGISTER(MIPS_F22, 82)
+CV_REGISTER(MIPS_F23, 83)
+CV_REGISTER(MIPS_F24, 84)
+CV_REGISTER(MIPS_F25, 85)
+CV_REGISTER(MIPS_F26, 86)
+CV_REGISTER(MIPS_F27, 87)
+CV_REGISTER(MIPS_F28, 88)
+CV_REGISTER(MIPS_F29, 89)
+CV_REGISTER(MIPS_F30, 90)
+CV_REGISTER(MIPS_F31, 91)
+CV_REGISTER(MIPS_Fsr, 92)
+
+#endif // defined(CV_REGISTERS_ALL) || defined(CV_REGISTERS_MIPS)
diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
@@ -123,6 +123,8 @@ static CPUType mapArchToCVCPUType(Triple::ArchType Type) {
     return CPUType::ARMNT;
   case Triple::ArchType::aarch64:
     return CPUType::ARM64;
+  case Triple::ArchType::mipsel:
+    return CPUType::MIPS;
   default:
     report_fatal_error("target architecture doesn't map to a CodeView CPUType");
   }
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
@@ -19,6 +19,7 @@
 #include "MipsMCNaCl.h"
 #include "MipsTargetStreamer.h"
 #include "TargetInfo/MipsTargetInfo.h"
+#include "llvm/DebugInfo/CodeView/CodeView.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCELFStreamer.h"
 #include "llvm/MC/MCInstrAnalysis.h"
@@ -44,6 +45,86 @@ using namespace llvm;
 #define GET_REGINFO_MC_DESC
 #include "MipsGenRegisterInfo.inc"
 
+void MIPS_MC::initLLVMToCVRegMapping(MCRegisterInfo *MRI) {
+  // Mapping from CodeView to MC register id.
+  static const struct {
+    codeview::RegisterId CVReg;
+    MCPhysReg Reg;
+  } RegMap[] = {
+      {codeview::RegisterId::MIPS_ZERO, Mips::ZERO},
+      {codeview::RegisterId::MIPS_AT, Mips::AT},
+      {codeview::RegisterId::MIPS_V0, Mips::V0},
+      {codeview::RegisterId::MIPS_V1, Mips::V1},
+      {codeview::RegisterId::MIPS_A0, Mips::A0},
+      {codeview::RegisterId::MIPS_A1, Mips::A1},
+      {codeview::RegisterId::MIPS_A2, Mips::A2},
+      {codeview::RegisterId::MIPS_A3, Mips::A3},
+      {codeview::RegisterId::MIPS_T0, Mips::T0},
+      {codeview::RegisterId::MIPS_T1, Mips::T1},
+      {codeview::RegisterId::MIPS_T2, Mips::T2},
+      {codeview::RegisterId::MIPS_T3, Mips::T3},
+      {codeview::RegisterId::MIPS_T4, Mips::T4},
+      {codeview::RegisterId::MIPS_T5, Mips::T5},
+      {codeview::RegisterId::MIPS_T6, Mips::T6},
+      {codeview::RegisterId::MIPS_T7, Mips::T7},
+      {codeview::RegisterId::MIPS_S0, Mips::S0},
+      {codeview::RegisterId::MIPS_S1, Mips::S1},
+      {codeview::RegisterId::MIPS_S2, Mips::S2},
+      {codeview::RegisterId::MIPS_S3, Mips::S3},
+      {codeview::RegisterId::MIPS_S4, Mips::S4},
+      {codeview::RegisterId::MIPS_S5, Mips::S5},
+      {codeview::RegisterId::MIPS_S6, Mips::S6},
+      {codeview::RegisterId::MIPS_S7, Mips::S7},
+      {codeview::RegisterId::MIPS_T8, Mips::T8},
+      {codeview::RegisterId::MIPS_T9, Mips::T9},
+      {codeview::RegisterId::MIPS_K0, Mips::K0},
+      {codeview::RegisterId::MIPS_K1, Mips::K1},
+      {codeview::RegisterId::MIPS_GP, Mips::GP},
+      {codeview::RegisterId::MIPS_SP, Mips::SP},
+      {codeview::RegisterId::MIPS_S8, Mips::FP},
+      {codeview::RegisterId::MIPS_RA, Mips::RA},
+      {codeview::RegisterId::MIPS_LO, Mips::HI0},
+      {codeview::RegisterId::MIPS_HI, Mips::LO0},
+      {codeview::RegisterId::MIPS_Fir, Mips::FCR0},
+      {codeview::RegisterId::MIPS_Psr, Mips::COP012}, // CP0.Status
+      {codeview::RegisterId::MIPS_F0, Mips::F0},
+      {codeview::RegisterId::MIPS_F1, Mips::F1},
+      {codeview::RegisterId::MIPS_F2, Mips::F2},
+      {codeview::RegisterId::MIPS_F3, Mips::F3},
+      {codeview::RegisterId::MIPS_F4, Mips::F4},
+      {codeview::RegisterId::MIPS_F5, Mips::F5},
+      {codeview::RegisterId::MIPS_F6, Mips::F6},
+      {codeview::RegisterId::MIPS_F7, Mips::F7},
+      {codeview::RegisterId::MIPS_F8, Mips::F8},
+      {codeview::RegisterId::MIPS_F9, Mips::F9},
+      {codeview::RegisterId::MIPS_F10, Mips::F10},
+      {codeview::RegisterId::MIPS_F11, Mips::F11},
+      {codeview::RegisterId::MIPS_F12, Mips::F12},
+      {codeview::RegisterId::MIPS_F13, Mips::F13},
+      {codeview::RegisterId::MIPS_F14, Mips::F14},
+      {codeview::RegisterId::MIPS_F15, Mips::F15},
+      {codeview::RegisterId::MIPS_F16, Mips::F16},
+      {codeview::RegisterId::MIPS_F17, Mips::F17},
+      {codeview::RegisterId::MIPS_F18, Mips::F18},
+      {codeview::RegisterId::MIPS_F19, Mips::F19},
+      {codeview::RegisterId::MIPS_F20, Mips::F20},
+      {codeview::RegisterId::MIPS_F21, Mips::F21},
+      {codeview::RegisterId::MIPS_F22, Mips::F22},
+      {codeview::RegisterId::MIPS_F23, Mips::F23},
+      {codeview::RegisterId::MIPS_F24, Mips::F24},
+      {codeview::RegisterId::MIPS_F25, Mips::F25},
+      {codeview::RegisterId::MIPS_F26, Mips::F26},
+      {codeview::RegisterId::MIPS_F27, Mips::F27},
+      {codeview::RegisterId::MIPS_F28, Mips::F28},
+      {codeview::RegisterId::MIPS_F29, Mips::F29},
+      {codeview::RegisterId::MIPS_F30, Mips::F30},
+      {codeview::RegisterId::MIPS_F31, Mips::F31},
+      {codeview::RegisterId::MIPS_Fsr, Mips::FCR31},
+  };
+  for (const auto &I : RegMap)
+    MRI->mapLLVMRegToCVReg(I.Reg, static_cast<int>(I.CVReg));
+}
+
 namespace {
 class MipsWinCOFFTargetStreamer : public MipsTargetStreamer {
 public:
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
@@ -57,6 +57,8 @@ createMipsELFObjectWriter(const Triple &TT, bool IsN32);
 std::unique_ptr<MCObjectTargetWriter> createMipsWinCOFFObjectWriter();
 
 namespace MIPS_MC {
+void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
+
 StringRef selectMipsCPU(const Triple &TT, StringRef CPU);
 }
 
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsWinCOFFObjectWriter.cpp
@@ -40,6 +40,10 @@ unsigned MipsWinCOFFObjectWriter::getRelocType(MCContext &Ctx,
   switch (FixupKind) {
   case FK_Data_4:
     return COFF::IMAGE_REL_MIPS_REFWORD;
+  case FK_SecRel_2:
+    return COFF::IMAGE_REL_MIPS_SECTION;
+  case FK_SecRel_4:
+    return COFF::IMAGE_REL_MIPS_SECREL;
   case Mips::fixup_Mips_26:
     return COFF::IMAGE_REL_MIPS_JMPADDR;
   case Mips::fixup_Mips_HI16:
diff --git a/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/llvm/lib/Target/Mips/MipsRegisterInfo.cpp
@@ -37,7 +37,9 @@ using namespace llvm;
 #define GET_REGINFO_TARGET_DESC
 #include "MipsGenRegisterInfo.inc"
 
-MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
+MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {
+  MIPS_MC::initLLVMToCVRegMapping(this);
+}
 
 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
 
diff --git a/llvm/test/MC/Mips/coff-relocs.ll b/llvm/test/MC/Mips/coff-relocs.ll
@@ -43,3 +43,39 @@ define i32 @foo_var() {
 ; CHECK:      - VirtualAddress:  0
 ; CHECK:        SymbolName:      var2
 ; CHECK:        Type:            IMAGE_REL_MIPS_REFWORD
+
+
+
+
+; CHECK:  - Name:            '.debug$S'
+; CHECK:    Relocations:
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, emissionKind: FullDebug)
+!1 = !DIFile(filename: "dummy.c", directory: "/tmp/private")
+!2 = !{i32 2, !"CodeView", i32 1}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 2}
+!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, scopeLine: 2, spFlags: DISPFlagDefinition, unit: !0)
+!6 = !DISubroutineType(types: !7)
+!7 = !{null}
+!8 = !DILocation(line: 3, scope: !5)
+
+define dso_local void @foo_dbg() #0 !dbg !5 {
+  ret void, !dbg !8
+; CHECK:      - VirtualAddress:  92
+; CHECK:        SymbolName:      foo_dbg
+; CHECK:        Type:            IMAGE_REL_MIPS_SECREL
+; CHECK:      - VirtualAddress:  96
+; CHECK:        SymbolName:      foo_dbg
+; CHECK:        Type:            IMAGE_REL_MIPS_SECTION
+; CHECK:      - VirtualAddress:  148
+; CHECK:        SymbolName:      foo_dbg
+; CHECK:        Type:            IMAGE_REL_MIPS_SECREL
+; CHECK:      - VirtualAddress:  152
+; CHECK:        SymbolName:      foo_dbg
+; CHECK:        Type:            IMAGE_REL_MIPS_SECTION
+}
+

Original file line number	Diff line number	Diff line change
`@@ -123,6 +123,8 @@ static CPUType mapArchToCVCPUType(Triple::ArchType Type) {`
`123`	`123`	`return CPUType::ARMNT;`
`124`	`124`	`case Triple::ArchType::aarch64:`
`125`	`125`	`return CPUType::ARM64;`
	`126`	`+ case Triple::ArchType::mipsel:`
	`127`	`+ return CPUType::MIPS;`
`126`	`128`	`default:`
`127`	`129`	`report_fatal_error("target architecture doesn't map to a CodeView CPUType");`
`128`	`130`	`}`
Original file line number	Diff line number	Diff line change
`@@ -57,6 +57,8 @@ createMipsELFObjectWriter(const Triple &TT, bool IsN32);`
`57`	`57`	`std::unique_ptr<MCObjectTargetWriter> createMipsWinCOFFObjectWriter();`
`58`	`58`
`59`	`59`	`namespace MIPS_MC {`
	`60`	`+void initLLVMToCVRegMapping(MCRegisterInfo *MRI);`
	`61`	`+`
`60`	`62`	`StringRef selectMipsCPU(const Triple &TT, StringRef CPU);`
`61`	`63`	`}`
`62`	`64`