comments

Author: Pierre-vh

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -28992,6 +28992,7 @@ static SDValue matchMergedBFX(SDValue Root, SelectionDAG &DAG,
 
   EVT VT = Root.getValueType();
 
+  // TODO: Support vectors?
   if (!VT.isScalarInteger() || Root.getOpcode() != ISD::AND)
     return SDValue();
 
@@ -29067,8 +29068,8 @@ SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
           TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL))
     return C;
 
-  if ((Cond == ISD::SETNE || Cond == ISD::SETEQ) &&
-      N0.getOpcode() == ISD::AND && isNullConstant(N1)) {
+  if (ISD::isIntEqualitySetCC(Cond) && N0.getOpcode() == ISD::AND &&
+      isNullConstant(N1)) {
 
     if (SDValue Res = matchMergedBFX(N0, DAG, TLI))
       return DAG.getSetCC(DL, VT, Res, N1, Cond);

llvm/test/CodeGen/AMDGPU/merged-bfx-opt.ll

@@ -100,3 +100,24 @@ entry:
   %cmp = icmp ne i32 %or1, 0
   ret i1 %cmp
 }
+
+define i1 @eq_i32_3x5_all_shifted(i32 %arg) {
+; CHECK-LABEL: eq_i32_3x5_all_shifted:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_and_b32_e32 v0, 0x7ffc, v0
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+entry:
+  %sh2 = lshr i32 %arg, 2
+  %a = and i32 %sh2, 31
+  %sh5 = lshr i32 %arg, 7
+  %b = and i32 %sh5, 31
+  %or = or i32 %a, %b
+  %sh10 = lshr i32 %arg, 10
+  %c = and i32 %sh10, 31
+  %or1 = or i32 %or, %c
+  %cmp = icmp ne i32 %or1, 0
+  ret i1 %cmp
+}