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[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
- Change InstrInfoEmitter to emit OpName as an enum class instead of an anonymous enum in the OpName namespace. - This will help clearly distinguish between values that are OpNames vs just operand indices and should help avoid bugs due to confusion between the two. - Rename OpName::OPERAND_LAST to NUM_OPERAND_NAMES. - Emit declaration of getOperandIdx() along with the OpName enum so it doesn't have to be repeated in various headers. - Also updated AMDGPU, RISCV, and WebAssembly backends to conform to the new definition of OpName (mostly mechanical changes).
1 parent 165a3d6 commit bee9664

26 files changed

+296
-222
lines changed

‎llvm/docs/WritingAnLLVMBackend.rst‎

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -954,8 +954,8 @@ Instruction Operand Name Mapping
954954
TableGen will also generate a function called getNamedOperandIdx() which
955955
can be used to look up an operand's index in a MachineInstr based on its
956956
TableGen name. Setting the UseNamedOperandTable bit in an instruction's
957-
TableGen definition will add all of its operands to an enumeration in the
958-
llvm::XXX:OpName namespace and also add an entry for it into the OperandMap
957+
TableGen definition will add all of its operands to an enumeration
958+
llvm::XXX:OpName and also add an entry for it into the OperandMap
959959
table, which can be queried using getNamedOperandIdx()
960960

961961
.. code-block:: text
@@ -978,20 +978,18 @@ XXXInstrInfo.cpp:
978978

979979
.. code-block:: c++
980980

981-
#define GET_INSTRINFO_NAMED_OPS // For getNamedOperandIdx() function
981+
// For getNamedOperandIdx() function definition.
982+
#define GET_INSTRINFO_NAMED_OPS
982983
#include "XXXGenInstrInfo.inc"
983984

984985
XXXInstrInfo.h:
985986

986987
.. code-block:: c++
987988

988-
#define GET_INSTRINFO_OPERAND_ENUM // For OpName enum
989+
// For OpName enum and getNamedOperandIdx declaration.
990+
#define GET_INSTRINFO_OPERAND_ENUM
989991
#include "XXXGenInstrInfo.inc"
990992

991-
namespace XXX {
992-
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
993-
} // End namespace XXX
994-
995993
Instruction Operand Types
996994
^^^^^^^^^^^^^^^^^^^^^^^^^
997995

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1783,7 +1783,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
17831783
bool validateMIMGMSAA(const MCInst &Inst);
17841784
bool validateOpSel(const MCInst &Inst);
17851785
bool validateTrue16OpSel(const MCInst &Inst);
1786-
bool validateNeg(const MCInst &Inst, int OpName);
1786+
bool validateNeg(const MCInst &Inst, AMDGPU::OpName OpName);
17871787
bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
17881788
bool validateVccOperand(MCRegister Reg) const;
17891789
bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
@@ -3959,8 +3959,9 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
39593959
const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
39603960
AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
39613961
int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
3962-
int RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
3963-
: AMDGPU::OpName::rsrc;
3962+
AMDGPU::OpName RSrcOpName = (Desc.TSFlags & SIInstrFlags::MIMG)
3963+
? AMDGPU::OpName::srsrc
3964+
: AMDGPU::OpName::rsrc;
39643965
int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RSrcOpName);
39653966
int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
39663967
int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);
@@ -4671,8 +4672,8 @@ bool AMDGPUAsmParser::validateTrue16OpSel(const MCInst &Inst) {
46714672
if (OpSelOpValue == 0)
46724673
return true;
46734674
unsigned OpCount = 0;
4674-
for (int OpName : {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
4675-
AMDGPU::OpName::src2, AMDGPU::OpName::vdst}) {
4675+
for (AMDGPU::OpName OpName : {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
4676+
AMDGPU::OpName::src2, AMDGPU::OpName::vdst}) {
46764677
int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), OpName);
46774678
if (OpIdx == -1)
46784679
continue;
@@ -4690,7 +4691,7 @@ bool AMDGPUAsmParser::validateTrue16OpSel(const MCInst &Inst) {
46904691
return true;
46914692
}
46924693

4693-
bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
4694+
bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, AMDGPU::OpName OpName) {
46944695
assert(OpName == AMDGPU::OpName::neg_lo || OpName == AMDGPU::OpName::neg_hi);
46954696

46964697
const unsigned Opc = Inst.getOpcode();
@@ -4715,9 +4716,9 @@ bool AMDGPUAsmParser::validateNeg(const MCInst &Inst, int OpName) {
47154716
// It is convenient that such instructions don't have src_modifiers operand
47164717
// for src operands that don't allow neg because they also don't allow opsel.
47174718

4718-
int SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
4719-
AMDGPU::OpName::src1_modifiers,
4720-
AMDGPU::OpName::src2_modifiers};
4719+
const AMDGPU::OpName SrcMods[3] = {AMDGPU::OpName::src0_modifiers,
4720+
AMDGPU::OpName::src1_modifiers,
4721+
AMDGPU::OpName::src2_modifiers};
47214722

47224723
for (unsigned i = 0; i < 3; ++i) {
47234724
if (!AMDGPU::hasNamedOperand(Opc, SrcMods[i])) {
@@ -4844,9 +4845,9 @@ bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
48444845
}
48454846

48464847
// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
4847-
static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
4848+
static int IsAGPROperand(const MCInst &Inst, AMDGPU::OpName Name,
48484849
const MCRegisterInfo *MRI) {
4849-
int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);
4850+
int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name);
48504851
if (OpIdx < 0)
48514852
return -1;
48524853

@@ -4867,12 +4868,13 @@ bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
48674868
SIInstrFlags::DS)) == 0)
48684869
return true;
48694870

4870-
uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
4871-
: AMDGPU::OpName::vdata;
4871+
AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS)
4872+
? AMDGPU::OpName::data0
4873+
: AMDGPU::OpName::vdata;
48724874

48734875
const MCRegisterInfo *MRI = getMRI();
48744876
int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);
4875-
int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);
4877+
int DataAreg = IsAGPROperand(Inst, DataName, MRI);
48764878

48774879
if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {
48784880
int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);
@@ -8703,9 +8705,8 @@ static void cvtVOP3DstOpSelOnly(MCInst &Inst, const MCRegisterInfo &MRI) {
87038705
return;
87048706

87058707
int SrcNum;
8706-
const int Ops[] = { AMDGPU::OpName::src0,
8707-
AMDGPU::OpName::src1,
8708-
AMDGPU::OpName::src2 };
8708+
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
8709+
AMDGPU::OpName::src2};
87098710
for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);
87108711
++SrcNum)
87118712
;
@@ -8827,12 +8828,11 @@ void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
88278828
if (OpSelIdx == -1)
88288829
return;
88298830

8830-
const int Ops[] = { AMDGPU::OpName::src0,
8831-
AMDGPU::OpName::src1,
8832-
AMDGPU::OpName::src2 };
8833-
const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
8834-
AMDGPU::OpName::src1_modifiers,
8835-
AMDGPU::OpName::src2_modifiers };
8831+
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
8832+
AMDGPU::OpName::src2};
8833+
const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
8834+
AMDGPU::OpName::src1_modifiers,
8835+
AMDGPU::OpName::src2_modifiers};
88368836

88378837
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
88388838

@@ -8968,12 +8968,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
89688968
if (NegHiIdx != -1)
89698969
addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
89708970

8971-
const int Ops[] = { AMDGPU::OpName::src0,
8972-
AMDGPU::OpName::src1,
8973-
AMDGPU::OpName::src2 };
8974-
const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
8975-
AMDGPU::OpName::src1_modifiers,
8976-
AMDGPU::OpName::src2_modifiers };
8971+
const AMDGPU::OpName Ops[] = {AMDGPU::OpName::src0, AMDGPU::OpName::src1,
8972+
AMDGPU::OpName::src2};
8973+
const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
8974+
AMDGPU::OpName::src1_modifiers,
8975+
AMDGPU::OpName::src2_modifiers};
89778976

89788977
unsigned OpSel = 0;
89798978
unsigned OpSelHi = 0;
@@ -9036,7 +9035,8 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
90369035
}
90379036

90389037
static void addSrcModifiersAndSrc(MCInst &Inst, const OperandVector &Operands,
9039-
unsigned i, unsigned Opc, unsigned OpName) {
9038+
unsigned i, unsigned Opc,
9039+
AMDGPU::OpName OpName) {
90409040
if (AMDGPU::getNamedOperandIdx(Opc, OpName) != -1)
90419041
((AMDGPUOperand &)*Operands[i]).addRegOrImmWithFPInputModsOperands(Inst, 2);
90429042
else

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 21 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -75,8 +75,8 @@ addOperand(MCInst &Inst, const MCOperand& Opnd) {
7575
}
7676

7777
static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
78-
uint16_t NameIdx) {
79-
int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
78+
AMDGPU::OpName Name) {
79+
int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), Name);
8080
if (OpIdx != -1) {
8181
auto *I = MI.begin();
8282
std::advance(I, OpIdx);
@@ -423,10 +423,11 @@ static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm,
423423
// are also tied.
424424
unsigned Opc = Inst.getOpcode();
425425
uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags;
426-
uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
427-
: AMDGPU::OpName::vdata;
426+
AMDGPU::OpName DataName = (TSFlags & SIInstrFlags::DS)
427+
? AMDGPU::OpName::data0
428+
: AMDGPU::OpName::vdata;
428429
const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo();
429-
int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx);
430+
int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataName);
430431
if ((int)Inst.getNumOperands() == DataIdx) {
431432
int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst);
432433
if (IsAGPROperand(Inst, DstIdx, MRI))
@@ -922,9 +923,9 @@ static VOPModifiers collectVOPModifiers(const MCInst &MI,
922923
bool IsVOP3P = false) {
923924
VOPModifiers Modifiers;
924925
unsigned Opc = MI.getOpcode();
925-
const int ModOps[] = {AMDGPU::OpName::src0_modifiers,
926-
AMDGPU::OpName::src1_modifiers,
927-
AMDGPU::OpName::src2_modifiers};
926+
const AMDGPU::OpName ModOps[] = {AMDGPU::OpName::src0_modifiers,
927+
AMDGPU::OpName::src1_modifiers,
928+
AMDGPU::OpName::src2_modifiers};
928929
for (int J = 0; J < 3; ++J) {
929930
int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
930931
if (OpIdx == -1)
@@ -951,15 +952,15 @@ void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const {
951952
const unsigned Opc = MI.getOpcode();
952953
const MCRegisterClass &ConversionRC =
953954
MRI.getRegClass(AMDGPU::VGPR_16RegClassID);
954-
constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = {
955-
{{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers,
956-
SISrcMods::OP_SEL_0},
957-
{AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers,
958-
SISrcMods::OP_SEL_0},
959-
{AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers,
960-
SISrcMods::OP_SEL_0},
961-
{AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers,
962-
SISrcMods::DST_OP_SEL}}};
955+
constexpr std::array<std::tuple<AMDGPU::OpName, AMDGPU::OpName, unsigned>, 4>
956+
OpAndOpMods = {{{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers,
957+
SISrcMods::OP_SEL_0},
958+
{AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers,
959+
SISrcMods::OP_SEL_0},
960+
{AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers,
961+
SISrcMods::OP_SEL_0},
962+
{AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers,
963+
SISrcMods::DST_OP_SEL}}};
963964
for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) {
964965
int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName);
965966
int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName);
@@ -1069,8 +1070,9 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
10691070
AMDGPU::OpName::vdata);
10701071
int VAddr0Idx =
10711072
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
1072-
int RsrcOpName = (TSFlags & SIInstrFlags::MIMG) ? AMDGPU::OpName::srsrc
1073-
: AMDGPU::OpName::rsrc;
1073+
AMDGPU::OpName RsrcOpName = (TSFlags & SIInstrFlags::MIMG)
1074+
? AMDGPU::OpName::srsrc
1075+
: AMDGPU::OpName::rsrc;
10741076
int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName);
10751077
int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
10761078
AMDGPU::OpName::dmask);

‎llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -70,9 +70,7 @@ class GCNDPPCombine {
7070
RegSubRegPair CombOldVGPR, bool CombBCZ,
7171
bool IsShrinkable) const;
7272

73-
bool hasNoImmOrEqual(MachineInstr &MI,
74-
unsigned OpndName,
75-
int64_t Value,
73+
bool hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName, int64_t Value,
7674
int64_t Mask = -1) const;
7775

7876
bool combineDPPMov(MachineInstr &MI) const;
@@ -513,7 +511,7 @@ MachineInstr *GCNDPPCombine::createDPPInst(
513511

514512
// returns true if MI doesn't have OpndName immediate operand or the
515513
// operand has Value
516-
bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, unsigned OpndName,
514+
bool GCNDPPCombine::hasNoImmOrEqual(MachineInstr &MI, AMDGPU::OpName OpndName,
517515
int64_t Value, int64_t Mask) const {
518516
auto *Imm = TII->getNamedOperand(MI, OpndName);
519517
if (!Imm)

‎llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1310,7 +1310,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
13101310
if (!SIInstrInfo::isVALU(*MI))
13111311
return false;
13121312

1313-
unsigned SDSTName;
1313+
AMDGPU::OpName SDSTName;
13141314
switch (MI->getOpcode()) {
13151315
case AMDGPU::V_READLANE_B32:
13161316
case AMDGPU::V_READFIRSTLANE_B32:

‎llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -308,7 +308,7 @@ bool AMDGPUCustomBehaviour::isVMEM(const MCInstrDesc &MCID) {
308308

309309
// taken from SIInstrInfo::hasModifiersSet()
310310
bool AMDGPUCustomBehaviour::hasModifiersSet(
311-
const std::unique_ptr<Instruction> &Inst, unsigned OpName) const {
311+
const std::unique_ptr<Instruction> &Inst, AMDGPU::OpName OpName) const {
312312
int Idx = AMDGPU::getNamedOperandIdx(Inst->getOpcode(), OpName);
313313
if (Idx == -1)
314314
return false;

‎llvm/lib/Target/AMDGPU/MCA/AMDGPUCustomBehaviour.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#ifndef LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H
1818
#define LLVM_LIB_TARGET_AMDGPU_MCA_AMDGPUCUSTOMBEHAVIOUR_H
1919

20+
#include "Utils/AMDGPUBaseInfo.h"
2021
#include "llvm/ADT/SmallVector.h"
2122
#include "llvm/MCA/CustomBehaviour.h"
2223
#include "llvm/TargetParser/TargetParser.h"
@@ -66,7 +67,7 @@ class AMDGPUCustomBehaviour : public CustomBehaviour {
6667
void generateWaitCntInfo();
6768
/// Helper function used in generateWaitCntInfo()
6869
bool hasModifiersSet(const std::unique_ptr<Instruction> &Inst,
69-
unsigned OpName) const;
70+
AMDGPU::OpName OpName) const;
7071
/// Helper function used in generateWaitCntInfo()
7172
bool isGWS(uint16_t Opcode) const;
7273
/// Helper function used in generateWaitCntInfo()

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1205,7 +1205,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
12051205
int NumOps = 0;
12061206
int Ops[3];
12071207

1208-
std::pair<int, int> MOps[] = {
1208+
std::pair<AMDGPU::OpName, AMDGPU::OpName> MOps[] = {
12091209
{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src0},
12101210
{AMDGPU::OpName::src1_modifiers, AMDGPU::OpName::src1},
12111211
{AMDGPU::OpName::src2_modifiers, AMDGPU::OpName::src2}};
@@ -1226,7 +1226,7 @@ void AMDGPUInstPrinter::printPackedModifier(const MCInst *MI,
12261226
MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsWMMA) {
12271227
NumOps = 0;
12281228
int DefaultValue = Mod == SISrcMods::OP_SEL_1;
1229-
for (int OpName :
1229+
for (AMDGPU::OpName OpName :
12301230
{AMDGPU::OpName::src0_modifiers, AMDGPU::OpName::src1_modifiers,
12311231
AMDGPU::OpName::src2_modifiers}) {
12321232
int Idx = AMDGPU::getNamedOperandIdx(Opc, OpName);

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -340,14 +340,13 @@ AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
340340

341341
uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
342342
using namespace AMDGPU::VOP3PEncoding;
343-
using namespace AMDGPU::OpName;
344343

345-
if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {
346-
if (AMDGPU::hasNamedOperand(Opcode, src2))
344+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::op_sel_hi)) {
345+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2))
347346
return 0;
348-
if (AMDGPU::hasNamedOperand(Opcode, src1))
347+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src1))
349348
return OP_SEL_HI_2;
350-
if (AMDGPU::hasNamedOperand(Opcode, src0))
349+
if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0))
351350
return OP_SEL_HI_1 | OP_SEL_HI_2;
352351
}
353352
return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@ createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI,
5050
#include "AMDGPUGenRegisterInfo.inc"
5151

5252
#define GET_INSTRINFO_ENUM
53-
#define GET_INSTRINFO_OPERAND_ENUM
5453
#define GET_INSTRINFO_MC_HELPER_DECLS
5554
#include "AMDGPUGenInstrInfo.inc"
5655

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