Skip to content

Commit bf5258b

Browse files
jrbyrnesjrbyrnes
committed
Revert "Use IMPLICIT_DEF instead of undef COPYs"
This reverts commit adff47f.
1 parent adff47f commit bf5258b

File tree

5 files changed

+68
-119
lines changed

5 files changed

+68
-119
lines changed

‎llvm/lib/CodeGen/InlineSpiller.cpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -946,6 +946,9 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
946946
if (MO.isUse() && !MO.readsReg() && !MO.isTied())
947947
continue;
948948

949+
if (MI->isCopy() && MI->getOperand(1).isUndef())
950+
continue;
951+
949952
if (MO.isImplicit()) {
950953
ImpReg = MO.getReg();
951954
continue;

‎llvm/lib/CodeGen/RegAllocBase.cpp‎

Lines changed: 1 addition & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,6 @@
2121
#include "llvm/CodeGen/MachineModuleInfo.h"
2222
#include "llvm/CodeGen/MachineRegisterInfo.h"
2323
#include "llvm/CodeGen/Spiller.h"
24-
#include "llvm/CodeGen/TargetInstrInfo.h"
2524
#include "llvm/CodeGen/TargetRegisterInfo.h"
2625
#include "llvm/CodeGen/VirtRegMap.h"
2726
#include "llvm/IR/DiagnosticInfo.h"
@@ -61,7 +60,6 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis,
6160
LiveRegMatrix &mat) {
6261
TRI = &vrm.getTargetRegInfo();
6362
MRI = &vrm.getRegInfo();
64-
TII = vrm.getMachineFunction().getSubtarget().getInstrInfo();
6563
VRM = &vrm;
6664
LIS = &lis;
6765
Matrix = &mat;
@@ -169,15 +167,9 @@ void RegAllocBase::cleanupFailedVReg(Register FailedReg, MCRegister PhysReg,
169167
// We still should produce valid IR. Kill all the uses and reduce the live
170168
// ranges so that we don't think it's possible to introduce kill flags later
171169
// which will fail the verifier.
172-
173-
SmallVector<MachineInstr *, 4> UndefCopies;
174-
175170
for (MachineOperand &MO : MRI->reg_operands(FailedReg)) {
176-
if (MO.readsReg()) {
171+
if (MO.readsReg())
177172
MO.setIsUndef(true);
178-
if (MO.getParent()->isCopy() && MO.isUse())
179-
UndefCopies.push_back(MO.getParent());
180-
}
181173
}
182174

183175
if (!MRI->isReserved(PhysReg)) {
@@ -188,22 +180,12 @@ void RegAllocBase::cleanupFailedVReg(Register FailedReg, MCRegister PhysReg,
188180
for (MachineOperand &MO : MRI->reg_operands(*Aliases)) {
189181
if (MO.readsReg()) {
190182
MO.setIsUndef(true);
191-
if (MO.getParent()->isCopy() && MO.isUse())
192-
UndefCopies.push_back(MO.getParent());
193183
LIS->removeAllRegUnitsForPhysReg(MO.getReg());
194184
}
195185
}
196186
}
197187
}
198188

199-
// If we have produced an undef copy, convert to IMPLICIT_DEF.
200-
for (MachineInstr *UndefCopy : UndefCopies) {
201-
assert(UndefCopy->isCopy() && UndefCopy->getNumOperands() == 2);
202-
const MCInstrDesc &Desc = TII->get(TargetOpcode::IMPLICIT_DEF);
203-
UndefCopy->removeOperand(1);
204-
UndefCopy->setDesc(Desc);
205-
}
206-
207189
// Directly perform the rewrite, and do not leave it to VirtRegRewriter as
208190
// usual. This avoids trying to manage illegal overlapping assignments in
209191
// LiveRegMatrix.

‎llvm/lib/CodeGen/RegAllocBase.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,6 @@ class RegAllocBase {
6565

6666
protected:
6767
const TargetRegisterInfo *TRI = nullptr;
68-
const TargetInstrInfo *TII = nullptr;
6968
MachineRegisterInfo *MRI = nullptr;
7069
VirtRegMap *VRM = nullptr;
7170
LiveIntervals *LIS = nullptr;

‎llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,8 +29,8 @@
2929
# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5)
3030
# CHECK-NEXT: [[RESTORE0:%[0-9]+]]:vreg_512_align2 = SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)
3131
# CHECK-NEXT: early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, [[RESTORE0]], 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit $exec
32-
# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = IMPLICIT_DEF {
33-
# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = IMPLICIT_DEF
32+
# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef $vgpr2_vgpr3 {
33+
# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef $vgpr0
3434
# CHECK-NEXT: }
3535
# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT0]].sub2_sub3 {
3636
# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0
@@ -120,8 +120,8 @@ body: |
120120
# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5)
121121
# CHECK-NEXT: [[RESTORE_0:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)
122122
# CHECK-NEXT: S_NOP 0, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit [[RESTORE_0]].sub0_sub1_sub2_sub3, implicit [[RESTORE_0]].sub4_sub5_sub6_sub7
123-
# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = IMPLICIT_DEF {
124-
# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = IMPLICIT_DEF
123+
# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef $vgpr2_vgpr3 {
124+
# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef $vgpr0
125125
# CHECK-NEXT: }
126126
# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY [[SPLIT0]].sub2_sub3 {
127127
# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0

‎llvm/test/CodeGen/AMDGPU/regalloc-undef-copy-fold.mir‎

Lines changed: 60 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -1,115 +1,80 @@
1-
# RUN: not llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs -start-before=greedy,1 -stop-after=virtregrewriter,2 -o - -verify-regalloc %s 2> %t.err | FileCheck %s
2-
# RUN: FileCheck -check-prefix=ERR %s < %t.err
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=amdgcn -mcpu=gfx908 -verify-machineinstrs --start-before=greedy,2 --stop-after=greedy,2 %s -o - | FileCheck %s
33

4-
# Make sure there's no machine verifier error after failure.
4+
# Make sure there's no machine verifier error
55

6-
# ERR: error: inline assembly requires more registers than available
7-
# ERR: error: inline assembly requires more registers than available
8-
# ERR: error: inline assembly requires more registers than available
9-
# ERR: error: inline assembly requires more registers than available
6+
# If RA is unable to find a register to allocate, then cleanupFailedVReg will do ad-hoc rewriting and will insert undefs to make the LiveRanges workable.
7+
# %30:av_128 = COPY undef $vgpr0_vgpr1_vgpr2_vgpr3 is an example of such a rewrite / undef. If we were to want to spill %30, we should not be inserting
8+
# actual spill code, as the source operand is undef.
9+
# Check that there are no verfier issues with the LiveRange of $vgpr0_vgpr1_vgpr2_vgpr3 / that we do not insert spill code for %30.
1010

11-
# This testcase cannot be compiled with the enforced register
12-
# budget. Previously, tryLastChanceRecoloring would assert here. It
13-
# was attempting to recolor a superregister with an overlapping
14-
# subregister over the same range.
1511

1612
--- |
17-
define void @dead_copy() #0 {
13+
define void @foo() #0 {
1814
ret void
1915
}
2016

21-
define void @copy_kill() #0 {
22-
ret void
23-
}
24-
25-
define void @copy_subreg() #0 {
26-
ret void
27-
}
28-
29-
define void @copy_subreg2() #0 {
30-
ret void
31-
}
32-
33-
attributes #0 = { "amdgpu-num-vgpr"="6" }
34-
35-
...
36-
37-
# CHECK-LABEL: name: dead_copy
38-
# CHECK: renamable $agpr0_agpr1_agpr2 = IMPLICIT_DEF
39-
# CHECK: dead renamable $vgpr0_vgpr1_vgpr2 = COPY renamable $agpr0_agpr1_agpr2
40-
41-
---
42-
name: dead_copy
43-
tracksRegLiveness: true
44-
machineFunctionInfo:
45-
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
46-
frameOffsetReg: '$sgpr33'
47-
stackPtrOffsetReg: '$sgpr32'
48-
body: |
49-
bb.0:
50-
51-
INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 11534346 /* regdef:VReg_512 */, def %0:vreg_512, 10158090 /* regdef:VReg_256 */, def %1:vreg_256, 4784138 /* regdef:VReg_128 */, def %2:vreg_128, 3670026 /* regdef:VReg_96 */, def %3:vreg_96, 3670026 /* regdef:VReg_96 */, def %4:vreg_96
52-
%5:vreg_96 = COPY %3
53-
INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %3
54-
SI_RETURN
55-
56-
...
57-
58-
59-
# CHECK-LABEL: name: copy_kill
60-
# CHECK: renamable $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF
17+
attributes #0 = { "amdgpu-waves-per-eu"="8,8" }
6118

62-
---
63-
name: copy_kill
64-
tracksRegLiveness: true
65-
machineFunctionInfo:
66-
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
67-
frameOffsetReg: '$sgpr33'
68-
stackPtrOffsetReg: '$sgpr32'
69-
body: |
70-
bb.0:
71-
72-
INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 11534346 /* regdef:VReg_512 */, def %0:vreg_512, 10158090 /* regdef:VReg_256 */, def %1:vreg_256, 4784138 /* regdef:VReg_128 */, def %2:vreg_128, 3670026 /* regdef:VReg_96 */, def %3:vreg_96, 3670026 /* regdef:VReg_96 */, def %4:vreg_96
73-
%5:vreg_96 = COPY %3
74-
INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %5
75-
SI_RETURN
7619
...
7720

78-
# CHECK-LABEL: name: copy_subreg
79-
# CHECK: renamable $vgpr1_vgpr2 = IMPLICIT_DEF
80-
# CHECK: renamable $vgpr0 = COPY renamable $vgpr1
8121
---
82-
name: copy_subreg
22+
name: foo
8323
tracksRegLiveness: true
24+
stack:
25+
- { id: 0, type: spill-slot, size: 32, alignment: 4 }
8426
machineFunctionInfo:
85-
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
86-
frameOffsetReg: '$sgpr33'
27+
maxKernArgAlign: 4
28+
isEntryFunction: true
29+
waveLimiter: true
30+
scratchRSrcReg: '$sgpr96_sgpr97_sgpr98_sgpr99'
8731
stackPtrOffsetReg: '$sgpr32'
32+
frameOffsetReg: '$sgpr33'
33+
hasSpilledVGPRs: true
34+
argumentInfo:
35+
privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
36+
dispatchPtr: { reg: '$sgpr4_sgpr5' }
37+
kernargSegmentPtr: { reg: '$sgpr6_sgpr7' }
38+
workGroupIDX: { reg: '$sgpr8' }
39+
privateSegmentWaveByteOffset: { reg: '$sgpr9' }
8840
body: |
8941
bb.0:
90-
91-
INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 11534346 /* regdef:VReg_512 */, def %0:vreg_512, 10158090 /* regdef:VReg_256 */, def %1:vreg_256, 4784138 /* regdef:VReg_128 */, def %2:vreg_128, 3670026 /* regdef:VReg_96 */, def %3:vreg_96, 3670026 /* regdef:VReg_96 */, def %4:vreg_96
92-
%3.sub0 = COPY %3.sub1
93-
INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %3
42+
; CHECK-LABEL: name: foo
43+
; CHECK: INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 10 /* regdef */, def %10, 10 /* regdef */, def %1, 10 /* regdef */, def %2, 10 /* regdef */, def $vgpr0_vgpr1_vgpr2_vgpr3, 10 /* regdef */, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
44+
; CHECK-NEXT: [[COPY:%[0-9]+]]:av_128 = COPY undef $vgpr0_vgpr1_vgpr2_vgpr3
45+
; CHECK-NEXT: SI_SPILL_AV128_SAVE [[COPY]], %stack.2, $sgpr32, 0, implicit $exec :: (store (s128) into %stack.2, align 4, addrspace 5)
46+
; CHECK-NEXT: SI_SPILL_AV160_SAVE %2, %stack.1, $sgpr32, 0, implicit $exec :: (store (s160) into %stack.1, align 4, addrspace 5)
47+
; CHECK-NEXT: SI_SPILL_AV256_SAVE %1, %stack.3, $sgpr32, 0, implicit $exec :: (store (s256) into %stack.3, align 4, addrspace 5)
48+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_512 = COPY %10
49+
; CHECK-NEXT: SI_SPILL_V512_SAVE [[COPY1]], %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5)
50+
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_512 = COPY $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
51+
; CHECK-NEXT: SI_SPILL_V512_SAVE [[COPY2]], %stack.6, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.6, align 4, addrspace 5)
52+
; CHECK-NEXT: INLINEASM &"; clobber", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
53+
; CHECK-NEXT: [[SI_SPILL_V512_RESTORE:%[0-9]+]]:vreg_512 = SI_SPILL_V512_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.6, align 4, addrspace 5)
54+
; CHECK-NEXT: $agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16 = COPY [[SI_SPILL_V512_RESTORE]]
55+
; CHECK-NEXT: [[SI_SPILL_V512_RESTORE1:%[0-9]+]]:vreg_512 = SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)
56+
; CHECK-NEXT: SI_SPILL_V512_SAVE [[SI_SPILL_V512_RESTORE1]], %stack.4, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.4, align 4, addrspace 5)
57+
; CHECK-NEXT: [[SI_SPILL_AV256_RESTORE:%[0-9]+]]:vreg_256 = SI_SPILL_AV256_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s256) from %stack.3, align 4, addrspace 5)
58+
; CHECK-NEXT: SI_SPILL_V256_SAVE [[SI_SPILL_AV256_RESTORE]], %stack.5, $sgpr32, 0, implicit $exec :: (store (s256) into %stack.5, align 4, addrspace 5)
59+
; CHECK-NEXT: [[SI_SPILL_AV160_RESTORE:%[0-9]+]]:vreg_160 = SI_SPILL_AV160_RESTORE %stack.1, $sgpr32, 0, implicit $exec :: (load (s160) from %stack.1, align 4, addrspace 5)
60+
; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_AV128_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s128) from %stack.2, align 4, addrspace 5)
61+
; CHECK-NEXT: [[SI_SPILL_AV512_RESTORE:%[0-9]+]]:av_512 = SI_SPILL_AV512_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.4, align 4, addrspace 5)
62+
; CHECK-NEXT: [[SI_SPILL_V256_RESTORE:%[0-9]+]]:vreg_256 = SI_SPILL_V256_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s256) from %stack.5, align 4, addrspace 5)
63+
; CHECK-NEXT: INLINEASM &"; use $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 9 /* reguse */, [[SI_SPILL_AV512_RESTORE]], 9 /* reguse */, [[SI_SPILL_V256_RESTORE]], 9 /* reguse */, [[SI_SPILL_AV160_RESTORE]], 9 /* reguse */, undef $vgpr0_vgpr1_vgpr2_vgpr3, 9 /* reguse */, $agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16
64+
; CHECK-NEXT: SI_RETURN
65+
INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 10, def %22:vreg_512, 10, def %25:vreg_256, 10, def %28:vreg_160, 10, def $vgpr0_vgpr1_vgpr2_vgpr3, 10, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
66+
%30:av_128 = COPY undef $vgpr0_vgpr1_vgpr2_vgpr3
67+
%27:av_160 = COPY %28:vreg_160
68+
%24:av_256 = COPY %25:vreg_256
69+
SI_SPILL_V512_SAVE %22:vreg_512, %stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4, addrspace 5)
70+
%18:vreg_512 = COPY $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
71+
INLINEASM &"; clobber", 1 /* sideeffect attdialect */, 10, implicit-def early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
72+
$agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16 = COPY %18:vreg_512
73+
%23:vreg_512 = SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4, addrspace 5)
74+
%26:vreg_256 = COPY %24:av_256
75+
%29:vreg_160 = COPY %27:av_160
76+
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %30:av_128
77+
INLINEASM &"; use $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 9, %23:vreg_512, 9, %26:vreg_256, 9, %29:vreg_160, 9, undef $vgpr0_vgpr1_vgpr2_vgpr3, 9, $agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16
9478
SI_RETURN
95-
...
96-
97-
# CHECK-LABEL: name: copy_subreg2
98-
# CHECK: renamable $vgpr0_vgpr1_vgpr2 = IMPLICIT_DEF
9979
100-
---
101-
name: copy_subreg2
102-
tracksRegLiveness: true
103-
machineFunctionInfo:
104-
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
105-
frameOffsetReg: '$sgpr33'
106-
stackPtrOffsetReg: '$sgpr32'
107-
body: |
108-
bb.0:
109-
110-
INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 11534346 /* regdef:VReg_512 */, def %0:vreg_512, 10158090 /* regdef:VReg_256 */, def %1:vreg_256, 4784138 /* regdef:VReg_128 */, def %2:vreg_128, 3670026 /* regdef:VReg_96 */, def %3:vreg_96, 3670026 /* regdef:VReg_96 */, def %4:vreg_96
111-
undef %5.sub0:vreg_96 = COPY %3.sub0
112-
%5.sub1_sub2:vreg_96 = COPY %3.sub1_sub2
113-
INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %5
114-
SI_RETURN
11580
...

0 commit comments

Comments
 (0)