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Formatting NFC.
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2 files changed

+15
-16
lines changed

2 files changed

+15
-16
lines changed

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -5521,12 +5521,11 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
55215521
LLT Ty = MRI.getType(DstReg);
55225522
unsigned Size = Ty.getSizeInBits();
55235523

5524-
unsigned SplitSize =
5525-
(IID == Intrinsic::amdgcn_update_dpp && (Size % 64 == 0) &&
5526-
ST.hasDPALU_DPP() &&
5527-
AMDGPU::isLegalDPALU_DPPControl(MI.getOperand(4).getImm()))
5528-
? 64
5529-
: 32;
5524+
unsigned SplitSize = 32;
5525+
if (IID == Intrinsic::amdgcn_update_dpp && (Size % 64 == 0) &&
5526+
ST.hasDPALU_DPP() &&
5527+
AMDGPU::isLegalDPALU_DPPControl(MI.getOperand(4).getImm()))
5528+
SplitSize = 64;
55305529

55315530
if (Size == SplitSize) {
55325531
// Already legal
@@ -5555,11 +5554,12 @@ bool AMDGPULegalizerInfo::legalizeLaneOp(LegalizerHelper &Helper,
55555554
if (Ty.isVector()) {
55565555
LLT EltTy = Ty.getElementType();
55575556
unsigned EltSize = EltTy.getSizeInBits();
5558-
if (EltSize == SplitSize)
5557+
if (EltSize == SplitSize) {
55595558
PartialResTy = EltTy;
5560-
else if (EltSize == 16 || EltSize == 32)
5561-
PartialResTy =
5562-
Ty.changeElementCount(ElementCount::getFixed(SplitSize / EltSize));
5559+
} else if (EltSize == 16 || EltSize == 32) {
5560+
unsigned NElem = SplitSize / EltSize;
5561+
PartialResTy = Ty.changeElementCount(ElementCount::getFixed(NElem));
5562+
}
55635563
// Handle all other cases via S32/S64 pieces;
55645564
}
55655565

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6164,12 +6164,11 @@ static SDValue lowerLaneOp(const SITargetLowering &TLI, SDNode *N,
61646164
MVT IntVT = MVT::getIntegerVT(ValSize);
61656165
const GCNSubtarget &ST =
61666166
DAG.getMachineFunction().getSubtarget<GCNSubtarget>();
6167-
unsigned SplitSize =
6168-
(IID == Intrinsic::amdgcn_update_dpp && (ValSize % 64 == 0) &&
6169-
ST.hasDPALU_DPP() &&
6170-
AMDGPU::isLegalDPALU_DPPControl(N->getConstantOperandVal(3)))
6171-
? 64
6172-
: 32;
6167+
unsigned SplitSize = 32;
6168+
if (IID == Intrinsic::amdgcn_update_dpp && (ValSize % 64 == 0) &&
6169+
ST.hasDPALU_DPP() &&
6170+
AMDGPU::isLegalDPALU_DPPControl(N->getConstantOperandVal(3)))
6171+
SplitSize = 64;
61736172

61746173
auto createLaneOp = [&DAG, &SL, N, IID](SDValue Src0, SDValue Src1,
61756174
SDValue Src2, MVT ValT) -> SDValue {

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