Update ARMISelLowering.cpp

Author: AZero13

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -20166,10 +20166,6 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
   if (!EnableOptimizeLogicalImm)
     return false;
 
-  // Only optimize AND for now.
-  if (Op.getOpcode() != ISD::AND)
-    return false;
-
   EVT VT = Op.getValueType();
 
   // Ignore vectors.
@@ -20182,22 +20178,56 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
   if (DemandedBits.popcount() == 32)
     return false;
 
+    // Only optimize AND for now.
+  if (Op.getOpcode() != ISD::AND)
+    return false;
+
   // Make sure the RHS really is a constant.
   ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
   if (!C)
     return false;
 
   unsigned Mask = C->getZExtValue();
+  
+  if (Mask == 0 || Mask == ~0U)
+    return false;
+    
+  unsigned Mask = C->getZExtValue();
 
   unsigned Demanded = DemandedBits.getZExtValue();
   unsigned ShrunkMask = Mask & Demanded;
   unsigned ExpandedMask = Mask | ~Demanded;
 
+    auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
+      return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;
+    };
+    auto UseMask = [Mask, Op, VT, &TLO](unsigned NewMask) -> bool {
+      if (NewMask == Mask)
+        return true;
+      SDLoc DL(Op);
+      SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT);
+      SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);
+      return TLO.CombineTo(Op, NewOp);
+    };
+
+      // If thumb, check for uxth and uxtb masks first and foremost.
+  if (Subtarget->isThumb1Only() && Subtarget->hasV6Ops()) {
+    if (IsLegalMask(0xFF)) {
+      ++NumOptimizedImms;
+      return UseMask(0xFF);
+    }
+
+    if (IsLegalMask(0xFFFF)) {
+      ++NumOptimizedImms;
+      return UseMask(0xFFFF);
+    }
+  }
+
   // If the mask is all zeros, let the target-independent code replace the
   // result with zero.
   if (ShrunkMask == 0) {
     ++NumOptimizedImms;
-    return false;
+    return UseMask(0);
   }
 
   // If the mask is all ones, erase the AND. (Currently, the target-independent
@@ -20208,30 +20238,6 @@ bool ARMTargetLowering::targetShrinkDemandedConstant(
     return TLO.CombineTo(Op, Op.getOperand(0));
   }
 
-  auto IsLegalMask = [ShrunkMask, ExpandedMask](unsigned Mask) -> bool {
-    return (ShrunkMask & Mask) == ShrunkMask && (~ExpandedMask & Mask) == 0;
-  };
-  auto UseMask = [Mask, Op, VT, &TLO](unsigned NewMask) -> bool {
-    if (NewMask == Mask)
-      return true;
-    SDLoc DL(Op);
-    SDValue NewC = TLO.DAG.getConstant(NewMask, DL, VT);
-    SDValue NewOp = TLO.DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), NewC);
-    return TLO.CombineTo(Op, NewOp);
-  };
-
-  // If thumb, check for uxth and uxtb masks first and foremost.
-  if (Subtarget->isThumb1Only() && Subtarget->hasV6Ops()) {
-    if (IsLegalMask(0xFF)) {
-      ++NumOptimizedImms;
-      return UseMask(0xFF);
-    }
-
-    if (IsLegalMask(0xFF00)) {
-      ++NumOptimizedImms;
-      return UseMask(0xFF00);
-    }
-  }
 
   if (isLegalLogicalImmediate(ShrunkMask, Subtarget)) {
     ++NumOptimizedImms;