[AMDGPU][True16][CodeGen] update zext pattern with reg_sequence (#154952)

update zext pattern with reg_sequence. This is a follow up from
#154211 (comment)

Author: broxigarchen

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -3106,9 +3106,7 @@ def : GCNPat<
 
 def : GCNPat<
   (i64 (DivergentUnaryFrag<zext> i16:$src)),
-  (REG_SEQUENCE VReg_64,
-    (INSERT_SUBREG (i32 (V_MOV_B32_e32 (i32 0))), VGPR_16:$src, lo16), sub0,
-    (S_MOV_B32 (i32 0)), sub1)
+  (REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (V_MOV_B32_e32 (i32 0)), sub1)
 >;
 
 def : GCNPat<