1+ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
12; RUN: opt -S -passes='dxil-legalize' -mtriple=dxil-pc-shadermodel6.3-library %s | FileCheck %s
23
34define void @const_i8_store () {
4- %accum.i.flat = alloca [1 x i32 ], align 4
5- %i = alloca i8 , align 4
6- store i8 1 , ptr %i
7- %i8.load = load i8 , ptr %i
8- %z = zext i8 %i8.load to i32
9- %gep = getelementptr i32 , ptr %accum.i.flat , i32 0
10- store i32 %z , ptr %gep , align 4
11- ret void
5+ ; CHECK-LABEL: define void @const_i8_store() {
6+ ; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4
7+ ; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4
8+ ; CHECK-NEXT: store i32 1, ptr [[TMP1]], align 4
9+ ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
10+ ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0
11+ ; CHECK-NEXT: store i32 [[TMP2]], ptr [[GEP]], align 4
12+ ; CHECK-NEXT: ret void
13+ ;
14+ %accum.i.flat = alloca [1 x i32 ], align 4
15+ %i = alloca i8 , align 4
16+ store i8 1 , ptr %i
17+ %i8.load = load i8 , ptr %i
18+ %z = zext i8 %i8.load to i32
19+ %gep = getelementptr i32 , ptr %accum.i.flat , i32 0
20+ store i32 %z , ptr %gep , align 4
21+ ret void
1222}
1323
1424define void @const_add_i8_store () {
15- %accum.i.flat = alloca [1 x i32 ], align 4
16- %i = alloca i8 , align 4
17- %add_i8 = add nsw i8 3 , 1
18- store i8 %add_i8 , ptr %i
19- %i8.load = load i8 , ptr %i
20- %z = zext i8 %i8.load to i32
21- %gep = getelementptr i32 , ptr %accum.i.flat , i32 0
22- store i32 %z , ptr %gep , align 4
23- ret void
25+ ; CHECK-LABEL: define void @const_add_i8_store() {
26+ ; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4
27+ ; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4
28+ ; CHECK-NEXT: store i32 4, ptr [[TMP1]], align 4
29+ ; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
30+ ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0
31+ ; CHECK-NEXT: store i32 [[TMP2]], ptr [[GEP]], align 4
32+ ; CHECK-NEXT: ret void
33+ ;
34+ %accum.i.flat = alloca [1 x i32 ], align 4
35+ %i = alloca i8 , align 4
36+ %add_i8 = add nsw i8 3 , 1
37+ store i8 %add_i8 , ptr %i
38+ %i8.load = load i8 , ptr %i
39+ %z = zext i8 %i8.load to i32
40+ %gep = getelementptr i32 , ptr %accum.i.flat , i32 0
41+ store i32 %z , ptr %gep , align 4
42+ ret void
2443}
2544
2645define void @var_i8_store (i1 %cmp.i8 ) {
27- %accum.i.flat = alloca [1 x i32 ], align 4
28- %i = alloca i8 , align 4
29- %select.i8 = select i1 %cmp.i8 , i8 1 , i8 2
30- store i8 %select.i8 , ptr %i
31- %i8.load = load i8 , ptr %i
32- %z = zext i8 %i8.load to i32
33- %gep = getelementptr i32 , ptr %accum.i.flat , i32 0
34- store i32 %z , ptr %gep , align 4
35- ret void
46+ ; CHECK-LABEL: define void @var_i8_store(
47+ ; CHECK-SAME: i1 [[CMP_I8:%.*]]) {
48+ ; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [1 x i32], align 4
49+ ; CHECK-NEXT: [[TMP1:%.*]] = alloca i32, align 4
50+ ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMP_I8]], i32 1, i32 2
51+ ; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4
52+ ; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP1]], align 4
53+ ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 0
54+ ; CHECK-NEXT: store i32 [[TMP3]], ptr [[GEP]], align 4
55+ ; CHECK-NEXT: ret void
56+ ;
57+ %accum.i.flat = alloca [1 x i32 ], align 4
58+ %i = alloca i8 , align 4
59+ %select.i8 = select i1 %cmp.i8 , i8 1 , i8 2
60+ store i8 %select.i8 , ptr %i
61+ %i8.load = load i8 , ptr %i
62+ %z = zext i8 %i8.load to i32
63+ %gep = getelementptr i32 , ptr %accum.i.flat , i32 0
64+ store i32 %z , ptr %gep , align 4
65+ ret void
3666}
3767
3868define void @conflicting_cast (i1 %cmp.i8 ) {
39- %accum.i.flat = alloca [2 x i32 ], align 4
40- %i = alloca i8 , align 4
41- %select.i8 = select i1 %cmp.i8 , i8 1 , i8 2
42- store i8 %select.i8 , ptr %i
43- %i8.load = load i8 , ptr %i
44- %z = zext i8 %i8.load to i16
45- %gep1 = getelementptr i16 , ptr %accum.i.flat , i32 0
46- store i16 %z , ptr %gep1 , align 2
47- %gep2 = getelementptr i16 , ptr %accum.i.flat , i32 1
48- store i16 %z , ptr %gep2 , align 2
49- %z2 = zext i8 %i8.load to i32
50- %gep3 = getelementptr i32 , ptr %accum.i.flat , i32 1
51- store i32 %z2 , ptr %gep3 , align 4
52- ret void
53- }
69+ ; CHECK-LABEL: define void @conflicting_cast(
70+ ; CHECK-SAME: i1 [[CMP_I8:%.*]]) {
71+ ; CHECK-NEXT: [[ACCUM_I_FLAT:%.*]] = alloca [2 x i32], align 4
72+ ; CHECK-NEXT: [[TMP1:%.*]] = alloca i16, align 2
73+ ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[CMP_I8]], i32 1, i32 2
74+ ; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP1]], align 4
75+ ; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[TMP1]], align 2
76+ ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i16, ptr [[ACCUM_I_FLAT]], i32 0
77+ ; CHECK-NEXT: store i16 [[TMP3]], ptr [[GEP1]], align 2
78+ ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i16, ptr [[ACCUM_I_FLAT]], i32 1
79+ ; CHECK-NEXT: store i16 [[TMP3]], ptr [[GEP2]], align 2
80+ ; CHECK-NEXT: [[TMP4:%.*]] = zext i16 [[TMP3]] to i32
81+ ; CHECK-NEXT: [[GEP3:%.*]] = getelementptr i32, ptr [[ACCUM_I_FLAT]], i32 1
82+ ; CHECK-NEXT: store i32 [[TMP4]], ptr [[GEP3]], align 4
83+ ; CHECK-NEXT: ret void
84+ ;
85+ %accum.i.flat = alloca [2 x i32 ], align 4
86+ %i = alloca i8 , align 4
87+ %select.i8 = select i1 %cmp.i8 , i8 1 , i8 2
88+ store i8 %select.i8 , ptr %i
89+ %i8.load = load i8 , ptr %i
90+ %z = zext i8 %i8.load to i16
91+ %gep1 = getelementptr i16 , ptr %accum.i.flat , i32 0
92+ store i16 %z , ptr %gep1 , align 2
93+ %gep2 = getelementptr i16 , ptr %accum.i.flat , i32 1
94+ store i16 %z , ptr %gep2 , align 2
95+ %z2 = zext i8 %i8.load to i32
96+ %gep3 = getelementptr i32 , ptr %accum.i.flat , i32 1
97+ store i32 %z2 , ptr %gep3 , align 4
98+ ret void
99+ }
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