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[PowerPC] Rename fp/int conversion nodes
PowerPC backend uses `FCFID*` and `FCTI(D|W)*` as custom ISD node name for in-place conversion between float and integers. But we do not always use these instructions. Also, separate nodes from int to f32/f64/f128 are not needed, since we can differentiate them by node types.
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5 files changed

+239
-271
lines changed

5 files changed

+239
-271
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp‎

Lines changed: 57 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -1668,14 +1668,18 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
16681668
case PPCISD::FSEL: return "PPCISD::FSEL";
16691669
case PPCISD::XSMAXC: return "PPCISD::XSMAXC";
16701670
case PPCISD::XSMINC: return "PPCISD::XSMINC";
1671-
case PPCISD::FCFID: return "PPCISD::FCFID";
1672-
case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
1673-
case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
1674-
case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
1675-
case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
1676-
case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
1677-
case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
1678-
case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
1671+
case PPCISD::SINT_TO_FP_INREG:
1672+
return "PPCISD::SINT_TO_FP_INREG";
1673+
case PPCISD::UINT_TO_FP_INREG:
1674+
return "PPCISD::UINT_TO_FP_INREG";
1675+
case PPCISD::FP_TO_I64_INREG:
1676+
return "PPCISD::FP_TO_I64_INREG";
1677+
case PPCISD::FP_TO_I32_INREG:
1678+
return "PPCISD::FP_TO_I32_INREG";
1679+
case PPCISD::FP_TO_U64_INREG:
1680+
return "PPCISD::FP_TO_U64_INREG";
1681+
case PPCISD::FP_TO_U32_INREG:
1682+
return "PPCISD::FP_TO_U32_INREG";
16791683
case PPCISD::FRE: return "PPCISD::FRE";
16801684
case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
16811685
case PPCISD::FTSQRT:
@@ -1810,22 +1814,18 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
18101814
case PPCISD::FNMSUB: return "PPCISD::FNMSUB";
18111815
case PPCISD::STRICT_FADDRTZ:
18121816
return "PPCISD::STRICT_FADDRTZ";
1813-
case PPCISD::STRICT_FCTIDZ:
1814-
return "PPCISD::STRICT_FCTIDZ";
1815-
case PPCISD::STRICT_FCTIWZ:
1816-
return "PPCISD::STRICT_FCTIWZ";
1817-
case PPCISD::STRICT_FCTIDUZ:
1818-
return "PPCISD::STRICT_FCTIDUZ";
1819-
case PPCISD::STRICT_FCTIWUZ:
1820-
return "PPCISD::STRICT_FCTIWUZ";
1821-
case PPCISD::STRICT_FCFID:
1822-
return "PPCISD::STRICT_FCFID";
1823-
case PPCISD::STRICT_FCFIDU:
1824-
return "PPCISD::STRICT_FCFIDU";
1825-
case PPCISD::STRICT_FCFIDS:
1826-
return "PPCISD::STRICT_FCFIDS";
1827-
case PPCISD::STRICT_FCFIDUS:
1828-
return "PPCISD::STRICT_FCFIDUS";
1817+
case PPCISD::STRICT_FP_TO_I64_INREG:
1818+
return "PPCISD::STRICT_FP_TO_I64_INREG";
1819+
case PPCISD::STRICT_FP_TO_I32_INREG:
1820+
return "PPCISD::STRICT_FP_TO_I32_INREG";
1821+
case PPCISD::STRICT_FP_TO_U64_INREG:
1822+
return "PPCISD::STRICT_FP_TO_U64_INREG";
1823+
case PPCISD::STRICT_FP_TO_U32_INREG:
1824+
return "PPCISD::STRICT_FP_TO_U32_INREG";
1825+
case PPCISD::STRICT_SINT_TO_FP_INREG:
1826+
return "PPCISD::STRICT_SINT_TO_FP_INREG";
1827+
case PPCISD::STRICT_UINT_TO_FP_INREG:
1828+
return "PPCISD::STRICT_UINT_TO_FP_INREG";
18291829
case PPCISD::LXVRZX: return "PPCISD::LXVRZX";
18301830
case PPCISD::STORE_COND:
18311831
return "PPCISD::STORE_COND";
@@ -8168,22 +8168,18 @@ static unsigned getPPCStrictOpcode(unsigned Opc) {
81688168
switch (Opc) {
81698169
default:
81708170
llvm_unreachable("No strict version of this opcode!");
8171-
case PPCISD::FCTIDZ:
8172-
return PPCISD::STRICT_FCTIDZ;
8173-
case PPCISD::FCTIWZ:
8174-
return PPCISD::STRICT_FCTIWZ;
8175-
case PPCISD::FCTIDUZ:
8176-
return PPCISD::STRICT_FCTIDUZ;
8177-
case PPCISD::FCTIWUZ:
8178-
return PPCISD::STRICT_FCTIWUZ;
8179-
case PPCISD::FCFID:
8180-
return PPCISD::STRICT_FCFID;
8181-
case PPCISD::FCFIDU:
8182-
return PPCISD::STRICT_FCFIDU;
8183-
case PPCISD::FCFIDS:
8184-
return PPCISD::STRICT_FCFIDS;
8185-
case PPCISD::FCFIDUS:
8186-
return PPCISD::STRICT_FCFIDUS;
8171+
case PPCISD::FP_TO_I64_INREG:
8172+
return PPCISD::STRICT_FP_TO_I64_INREG;
8173+
case PPCISD::FP_TO_I32_INREG:
8174+
return PPCISD::STRICT_FP_TO_I32_INREG;
8175+
case PPCISD::FP_TO_U64_INREG:
8176+
return PPCISD::STRICT_FP_TO_U64_INREG;
8177+
case PPCISD::FP_TO_U32_INREG:
8178+
return PPCISD::STRICT_FP_TO_U32_INREG;
8179+
case PPCISD::SINT_TO_FP_INREG:
8180+
return PPCISD::STRICT_SINT_TO_FP_INREG;
8181+
case PPCISD::UINT_TO_FP_INREG:
8182+
return PPCISD::STRICT_UINT_TO_FP_INREG;
81878183
}
81888184
}
81898185

@@ -8221,13 +8217,14 @@ static SDValue convertFPToInt(SDValue Op, SelectionDAG &DAG,
82218217
switch (DestTy.SimpleTy) {
82228218
default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
82238219
case MVT::i32:
8224-
Opc = IsSigned ? PPCISD::FCTIWZ
8225-
: (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ);
8220+
Opc = IsSigned ? PPCISD::FP_TO_I32_INREG
8221+
: (Subtarget.hasFPCVT() ? PPCISD::FP_TO_U32_INREG
8222+
: PPCISD::FP_TO_I64_INREG);
82268223
break;
82278224
case MVT::i64:
82288225
assert((IsSigned || Subtarget.hasFPCVT()) &&
82298226
"i64 FP_TO_UINT is supported only with FPCVT");
8230-
Opc = IsSigned ? PPCISD::FCTIDZ : PPCISD::FCTIDUZ;
8227+
Opc = IsSigned ? PPCISD::FP_TO_I64_INREG : PPCISD::FP_TO_U64_INREG;
82318228
}
82328229
EVT ConvTy = Src.getValueType() == MVT::f128 ? MVT::f128 : MVT::f64;
82338230
SDValue Conv;
@@ -8528,8 +8525,8 @@ static SDValue convertIntToFP(SDValue Op, SDValue Src, SelectionDAG &DAG,
85288525
// If we have FCFIDS, then use it when converting to single-precision.
85298526
// Otherwise, convert to double-precision and then round.
85308527
bool IsSingle = Op.getValueType() == MVT::f32 && Subtarget.hasFPCVT();
8531-
unsigned ConvOpc = IsSingle ? (IsSigned ? PPCISD::FCFIDS : PPCISD::FCFIDUS)
8532-
: (IsSigned ? PPCISD::FCFID : PPCISD::FCFIDU);
8528+
unsigned ConvOpc =
8529+
IsSigned ? PPCISD::SINT_TO_FP_INREG : PPCISD::UINT_TO_FP_INREG;
85338530
EVT ConvTy = IsSingle ? MVT::f32 : MVT::f64;
85348531
if (Op->isStrictFPOpcode()) {
85358532
if (!Chain)
@@ -14469,13 +14466,13 @@ combineElementTruncationToVectorTruncation(SDNode *N,
1446914466
// This combine happens after legalization so the fp_to_[su]i nodes are
1447014467
// already converted to PPCSISD nodes.
1447114468
unsigned FirstConversion = FirstInput.getOperand(0).getOpcode();
14472-
if (FirstConversion == PPCISD::FCTIDZ ||
14473-
FirstConversion == PPCISD::FCTIDUZ ||
14474-
FirstConversion == PPCISD::FCTIWZ ||
14475-
FirstConversion == PPCISD::FCTIWUZ) {
14469+
if (FirstConversion == PPCISD::FP_TO_I64_INREG ||
14470+
FirstConversion == PPCISD::FP_TO_U64_INREG ||
14471+
FirstConversion == PPCISD::FP_TO_I32_INREG ||
14472+
FirstConversion == PPCISD::FP_TO_U32_INREG) {
1447614473
bool IsSplat = true;
14477-
bool Is32Bit = FirstConversion == PPCISD::FCTIWZ ||
14478-
FirstConversion == PPCISD::FCTIWUZ;
14474+
bool Is32Bit = FirstConversion == PPCISD::FP_TO_I32_INREG ||
14475+
FirstConversion == PPCISD::FP_TO_U32_INREG;
1447914476
EVT SrcVT = FirstInput.getOperand(0).getValueType();
1448014477
SmallVector<SDValue, 4> Ops;
1448114478
EVT TargetVT = N->getValueType(0);
@@ -14521,8 +14518,8 @@ combineElementTruncationToVectorTruncation(SDNode *N,
1452114518
}
1452214519

1452314520
unsigned Opcode;
14524-
if (FirstConversion == PPCISD::FCTIDZ ||
14525-
FirstConversion == PPCISD::FCTIWZ)
14521+
if (FirstConversion == PPCISD::FP_TO_I64_INREG ||
14522+
FirstConversion == PPCISD::FP_TO_I32_INREG)
1452614523
Opcode = ISD::FP_TO_SINT;
1452714524
else
1452814525
Opcode = ISD::FP_TO_UINT;
@@ -14932,9 +14929,8 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
1493214929
if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) {
1493314930
bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
1493414931
bool DstDouble = Op.getValueType() == MVT::f64;
14935-
unsigned ConvOp = Signed ?
14936-
(DstDouble ? PPCISD::FCFID : PPCISD::FCFIDS) :
14937-
(DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS);
14932+
unsigned ConvOp =
14933+
Signed ? PPCISD::SINT_TO_FP_INREG : PPCISD::UINT_TO_FP_INREG;
1493814934
SDValue WidthConst =
1493914935
DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2,
1494014936
dl, false);
@@ -14966,11 +14962,8 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
1496614962

1496714963
// If we have FCFIDS, then use it when converting to single-precision.
1496814964
// Otherwise, convert to double-precision and then round.
14969-
unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
14970-
? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
14971-
: PPCISD::FCFIDS)
14972-
: (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
14973-
: PPCISD::FCFID);
14965+
unsigned FCFOp = Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::UINT_TO_FP_INREG
14966+
: PPCISD::SINT_TO_FP_INREG;
1497414967
MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
1497514968
? MVT::f32
1497614969
: MVT::f64;
@@ -14989,9 +14982,9 @@ SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
1498914982
return SDValue();
1499014983
}
1499114984

14992-
unsigned FCTOp =
14993-
Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
14994-
PPCISD::FCTIDUZ;
14985+
unsigned FCTOp = Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT
14986+
? PPCISD::FP_TO_I64_INREG
14987+
: PPCISD::FP_TO_U64_INREG;
1499514988

1499614989
SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
1499714990
SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);

‎llvm/lib/Target/PowerPC/PPCISelLowering.h‎

Lines changed: 15 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -56,27 +56,15 @@ namespace llvm {
5656
XSMAXC,
5757
XSMINC,
5858

59-
/// FCFID - The FCFID instruction, taking an f64 operand and producing
60-
/// and f64 value containing the FP representation of the integer that
61-
/// was temporarily in the f64 operand.
62-
FCFID,
63-
64-
/// Newer FCFID[US] integer-to-floating-point conversion instructions for
65-
/// unsigned integers and single-precision outputs.
66-
FCFIDU,
67-
FCFIDS,
68-
FCFIDUS,
69-
70-
/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
71-
/// operand, producing an f64 value containing the integer representation
72-
/// of that FP value.
73-
FCTIDZ,
74-
FCTIWZ,
75-
76-
/// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
77-
/// unsigned integers with round toward zero.
78-
FCTIDUZ,
79-
FCTIWUZ,
59+
/// Inplace integer-to-float conversion.
60+
SINT_TO_FP_INREG,
61+
UINT_TO_FP_INREG,
62+
63+
/// Inplace float-to-integer conversion.
64+
FP_TO_I64_INREG,
65+
FP_TO_I32_INREG,
66+
FP_TO_U64_INREG,
67+
FP_TO_U32_INREG,
8068

8169
/// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
8270
/// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
@@ -476,16 +464,14 @@ namespace llvm {
476464
XXMFACC,
477465

478466
// Constrained conversion from floating point to int
479-
STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE,
480-
STRICT_FCTIWZ,
481-
STRICT_FCTIDUZ,
482-
STRICT_FCTIWUZ,
467+
STRICT_FP_TO_I64_INREG = ISD::FIRST_TARGET_STRICTFP_OPCODE,
468+
STRICT_FP_TO_I32_INREG,
469+
STRICT_FP_TO_U64_INREG,
470+
STRICT_FP_TO_U32_INREG,
483471

484472
/// Constrained integer-to-floating-point conversion instructions.
485-
STRICT_FCFID,
486-
STRICT_FCFIDU,
487-
STRICT_FCFIDS,
488-
STRICT_FCFIDUS,
473+
STRICT_SINT_TO_FP_INREG,
474+
STRICT_UINT_TO_FP_INREG,
489475

490476
/// Constrained floating point add in round-to-zero mode.
491477
STRICT_FADDRTZ,

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1800,7 +1800,7 @@ let PPC970_Unit = 3, hasSideEffects = 0, mayRaiseFPException = 1,
18001800
Uses = [RM] in { // FPU Operations.
18011801
defm FCFID : XForm_26r<63, 846, (outs f8rc:$RST), (ins f8rc:$RB),
18021802
"fcfid", "$RST, $RB", IIC_FPGeneral,
1803-
[(set f64:$RST, (PPCany_fcfid f64:$RB))]>, isPPC64;
1803+
[(set f64:$RST, (PPCany_sint_to_fp f64:$RB))]>, isPPC64;
18041804
defm FCTID : XForm_26r<63, 814, (outs f8rc:$RST), (ins f8rc:$RB),
18051805
"fctid", "$RST, $RB", IIC_FPGeneral,
18061806
[]>, isPPC64;
@@ -1809,23 +1809,23 @@ defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$RST), (ins f8rc:$RB),
18091809
[]>, isPPC64;
18101810
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$RST), (ins f8rc:$RB),
18111811
"fctidz", "$RST, $RB", IIC_FPGeneral,
1812-
[(set f64:$RST, (PPCany_fctidz f64:$RB))]>, isPPC64;
1812+
[(set f64:$RST, (PPCany_fp_to_i64 f64:$RB))]>, isPPC64;
18131813

18141814
defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$RST), (ins f8rc:$RB),
18151815
"fcfidu", "$RST, $RB", IIC_FPGeneral,
1816-
[(set f64:$RST, (PPCany_fcfidu f64:$RB))]>, isPPC64;
1816+
[(set f64:$RST, (PPCany_uint_to_fp f64:$RB))]>, isPPC64;
18171817
defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$RST), (ins f8rc:$RB),
18181818
"fcfids", "$RST, $RB", IIC_FPGeneral,
1819-
[(set f32:$RST, (PPCany_fcfids f64:$RB))]>, isPPC64;
1819+
[(set f32:$RST, (PPCany_sint_to_fp f64:$RB))]>, isPPC64;
18201820
defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$RST), (ins f8rc:$RB),
18211821
"fcfidus", "$RST, $RB", IIC_FPGeneral,
1822-
[(set f32:$RST, (PPCany_fcfidus f64:$RB))]>, isPPC64;
1822+
[(set f32:$RST, (PPCany_uint_to_fp f64:$RB))]>, isPPC64;
18231823
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$RST), (ins f8rc:$RB),
18241824
"fctiduz", "$RST, $RB", IIC_FPGeneral,
1825-
[(set f64:$RST, (PPCany_fctiduz f64:$RB))]>, isPPC64;
1825+
[(set f64:$RST, (PPCany_fp_to_u64 f64:$RB))]>, isPPC64;
18261826
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$RST), (ins f8rc:$RB),
18271827
"fctiwuz", "$RST, $RB", IIC_FPGeneral,
1828-
[(set f64:$RST, (PPCany_fctiwuz f64:$RB))]>, isPPC64;
1828+
[(set f64:$RST, (PPCany_fp_to_u32 f64:$RB))]>, isPPC64;
18291829
}
18301830

18311831
// These instructions store a hash computed from the value of the link register

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