fixup! [RISCV] Toggle throttled FP64 feature in SiFive7 scheduling model with subtarget feature

mshockwave · mshockwave · commit c10322f62ecd · 2025-10-09T17:34:12.000-07:00
diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td
@@ -14,6 +14,8 @@
 // otherwise.
 def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>;
 
+// This scheduling predicate is true when subtarget feature TuneHasThrottledVecFP64
+// is enabled.
 def ThrottledVecFP64SchedPred : FeatureSchedPredicate<TuneHasThrottledVecFP64>;
 
 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -338,8 +338,8 @@ def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390",
                                        FeatureStdExtZvl1024b,
                                        FeatureVendorXSiFivecdiscarddlone,
                                        FeatureVendorXSiFivecflushdlone],
-                                       !listconcat(SiFiveIntelligenceTuneFeatures,
-                                                   [TuneHasThrottledVecFP64])>;
+                                      !listconcat(SiFiveIntelligenceTuneFeatures,
+                                                  [TuneHasThrottledVecFP64])>;
 
 defvar SiFiveP400TuneFeatures = [TuneNoDefaultUnroll,
                                  TuneConditionalCompressedMoveFusion,
