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[MC][AArch64] Enable '+v8a' when nothing specified for MCSubtargetInfo
Since D110065, the 'R' profile support is added to LLVM. It turns the `generic` cpu into the intersection of v8-a and v8-r. However, this makes some backward compatibility problems. The original patch makes the clang driver implicitly pass -march=armv8-a when only the triple is specified. Since it only applies to clang, other tools like llvm-objdump still faces the backward compatibility problem. This patch applies the same idea to MC related tools by enabling '+v8a' feature when nothing is specified (both CPU and FS are empty) for MCSubtargetInfo creation. This patch should fix PR53956. Reviewed by: labrinea Differential Revision: https://reviews.llvm.org/D124319 (cherry picked from commit 4a31af8)
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‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,8 @@ static MCSubtargetInfo *
5252
createAArch64MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
5353
if (CPU.empty()) {
5454
CPU = "generic";
55+
if (FS.empty())
56+
FS = "+v8a";
5557

5658
if (TT.isArm64e())
5759
CPU = "apple-a12";

‎llvm/test/MC/AArch64/arm64-branch-encoding.s‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,17 +137,23 @@ L1:
137137
; CHECK: encoding: [0x41,0x00,0xa0,0xd4]
138138
dcps2 #3
139139
; CHECK: encoding: [0x62,0x00,0xa0,0xd4]
140+
dcps3 #4
141+
; CHECK: encoding: [0x83,0x00,0xa0,0xd4]
140142
hlt #5
141143
; CHECK: encoding: [0xa0,0x00,0x40,0xd4]
142144
hvc #6
143145
; CHECK: encoding: [0xc2,0x00,0x00,0xd4]
146+
smc #7
147+
; CHECK: encoding: [0xe3,0x00,0x00,0xd4]
144148
svc #8
145149
; CHECK: encoding: [0x01,0x01,0x00,0xd4]
146150

147151
; The immediate defaults to zero for DCPSn
148152
dcps1
149153
dcps2
154+
dcps3
150155

151156
; CHECK: dcps1 ; encoding: [0x01,0x00,0xa0,0xd4]
152157
; CHECK: dcps2 ; encoding: [0x02,0x00,0xa0,0xd4]
158+
; CHECK: dcps3 ; encoding: [0x03,0x00,0xa0,0xd4]
153159

‎llvm/test/MC/AArch64/arm64-system-encoding.s‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@ foo:
123123
msr TPIDR_EL2, x3
124124
msr TPIDR_EL3, x3
125125
msr TTBR0_EL1, x3
126+
msr TTBR0_EL2, x3
126127
msr TTBR0_EL3, x3
127128
msr TTBR1_EL1, x3
128129
msr VBAR_EL1, x3
@@ -131,6 +132,7 @@ foo:
131132
msr VMPIDR_EL2, x3
132133
msr VPIDR_EL2, x3
133134
msr VTCR_EL2, x3
135+
msr VTTBR_EL2, x3
134136
msr SPSel, x3
135137
msr S3_2_C11_C6_4, x1
136138
msr S0_0_C0_C0_0, x0
@@ -200,6 +202,7 @@ foo:
200202
; CHECK: msr TPIDR_EL2, x3 ; encoding: [0x43,0xd0,0x1c,0xd5]
201203
; CHECK: msr TPIDR_EL3, x3 ; encoding: [0x43,0xd0,0x1e,0xd5]
202204
; CHECK: msr TTBR0_EL1, x3 ; encoding: [0x03,0x20,0x18,0xd5]
205+
; CHECK: msr TTBR0_EL2, x3 ; encoding: [0x03,0x20,0x1c,0xd5]
203206
; CHECK: msr TTBR0_EL3, x3 ; encoding: [0x03,0x20,0x1e,0xd5]
204207
; CHECK: msr TTBR1_EL1, x3 ; encoding: [0x23,0x20,0x18,0xd5]
205208
; CHECK: msr VBAR_EL1, x3 ; encoding: [0x03,0xc0,0x18,0xd5]
@@ -208,6 +211,7 @@ foo:
208211
; CHECK: msr VMPIDR_EL2, x3 ; encoding: [0xa3,0x00,0x1c,0xd5]
209212
; CHECK: msr VPIDR_EL2, x3 ; encoding: [0x03,0x00,0x1c,0xd5]
210213
; CHECK: msr VTCR_EL2, x3 ; encoding: [0x43,0x21,0x1c,0xd5]
214+
; CHECK: msr VTTBR_EL2, x3 ; encoding: [0x03,0x21,0x1c,0xd5]
211215
; CHECK: msr SPSel, x3 ; encoding: [0x03,0x42,0x18,0xd5]
212216
; CHECK: msr S3_2_C11_C6_4, x1 ; encoding: [0x81,0xb6,0x1a,0xd5]
213217
; CHECK: msr S0_0_C0_C0_0, x0 ; encoding: [0x00,0x00,0x00,0xd5]
@@ -309,6 +313,7 @@ foo:
309313
mrs x3, TPIDR_EL2
310314
mrs x3, TPIDR_EL3
311315
mrs x3, TTBR0_EL1
316+
mrs x3, TTBR0_EL2
312317
mrs x3, TTBR0_EL3
313318
mrs x3, TTBR1_EL1
314319
mrs x3, VBAR_EL1
@@ -317,6 +322,7 @@ foo:
317322
mrs x3, VMPIDR_EL2
318323
mrs x3, VPIDR_EL2
319324
mrs x3, VTCR_EL2
325+
mrs x3, VTTBR_EL2
320326

321327
mrs x3, MDCCSR_EL0
322328
mrs x3, MDCCINT_EL1
@@ -494,6 +500,7 @@ foo:
494500
; CHECK: mrs x3, TPIDR_EL2 ; encoding: [0x43,0xd0,0x3c,0xd5]
495501
; CHECK: mrs x3, TPIDR_EL3 ; encoding: [0x43,0xd0,0x3e,0xd5]
496502
; CHECK: mrs x3, TTBR0_EL1 ; encoding: [0x03,0x20,0x38,0xd5]
503+
; CHECK: mrs x3, TTBR0_EL2 ; encoding: [0x03,0x20,0x3c,0xd5]
497504
; CHECK: mrs x3, TTBR0_EL3 ; encoding: [0x03,0x20,0x3e,0xd5]
498505
; CHECK: mrs x3, TTBR1_EL1 ; encoding: [0x23,0x20,0x38,0xd5]
499506
; CHECK: mrs x3, VBAR_EL1 ; encoding: [0x03,0xc0,0x38,0xd5]
@@ -502,6 +509,7 @@ foo:
502509
; CHECK: mrs x3, VMPIDR_EL2 ; encoding: [0xa3,0x00,0x3c,0xd5]
503510
; CHECK: mrs x3, VPIDR_EL2 ; encoding: [0x03,0x00,0x3c,0xd5]
504511
; CHECK: mrs x3, VTCR_EL2 ; encoding: [0x43,0x21,0x3c,0xd5]
512+
; CHECK: mrs x3, VTTBR_EL2 ; encoding: [0x03,0x21,0x3c,0xd5]
505513
; CHECK: mrs x3, MDCCSR_EL0 ; encoding: [0x03,0x01,0x33,0xd5]
506514
; CHECK: mrs x3, MDCCINT_EL1 ; encoding: [0x03,0x02,0x30,0xd5]
507515
; CHECK: mrs x3, DBGDTR_EL0 ; encoding: [0x03,0x04,0x33,0xd5]

‎llvm/test/MC/AArch64/basic-a64-instructions.s‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 %s | FileCheck %s
1+
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8a,+fp-armv8 %s | FileCheck %s
22
.globl _func
33

44
// Check that the assembler can handle the documented syntax from the ARM ARM.
@@ -1694,21 +1694,27 @@ _func:
16941694
// CHECK: svc #{{65535|0xffff}} // encoding: [0xe1,0xff,0x1f,0xd4]
16951695

16961696
hvc #1
1697+
smc #12000
16971698
brk #12
16981699
hlt #123
16991700
// CHECK: hvc #{{1|0x1}} // encoding: [0x22,0x00,0x00,0xd4]
1701+
// CHECK: smc #{{12000|0x2ee0}} // encoding: [0x03,0xdc,0x05,0xd4]
17001702
// CHECK: brk #{{12|0xc}} // encoding: [0x80,0x01,0x20,0xd4]
17011703
// CHECK: hlt #{{123|0x7b}} // encoding: [0x60,0x0f,0x40,0xd4]
17021704

17031705
dcps1 #42
17041706
dcps2 #9
1707+
dcps3 #1000
17051708
// CHECK: dcps1 #{{42|0x2a}} // encoding: [0x41,0x05,0xa0,0xd4]
17061709
// CHECK: dcps2 #{{9|0x9}} // encoding: [0x22,0x01,0xa0,0xd4]
1710+
// CHECK: dcps3 #{{1000|0x3e8}} // encoding: [0x03,0x7d,0xa0,0xd4]
17071711

17081712
dcps1
17091713
dcps2
1714+
dcps3
17101715
// CHECK: dcps1 // encoding: [0x01,0x00,0xa0,0xd4]
17111716
// CHECK: dcps2 // encoding: [0x02,0x00,0xa0,0xd4]
1717+
// CHECK: dcps3 // encoding: [0x03,0x00,0xa0,0xd4]
17121718

17131719
//------------------------------------------------------------------------------
17141720
// Extract (immediate)
@@ -3779,11 +3785,13 @@ _func:
37793785
msr HACR_EL2, x12
37803786
msr MDCR_EL3, x12
37813787
msr TTBR0_EL1, x12
3788+
msr TTBR0_EL2, x12
37823789
msr TTBR0_EL3, x12
37833790
msr TTBR1_EL1, x12
37843791
msr TCR_EL1, x12
37853792
msr TCR_EL2, x12
37863793
msr TCR_EL3, x12
3794+
msr VTTBR_EL2, x12
37873795
msr VTCR_EL2, x12
37883796
msr DACR32_EL2, x12
37893797
msr SPSR_EL1, x12
@@ -4031,11 +4039,13 @@ _func:
40314039
// CHECK: msr {{hacr_el2|HACR_EL2}}, x12 // encoding: [0xec,0x11,0x1c,0xd5]
40324040
// CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12 // encoding: [0x2c,0x13,0x1e,0xd5]
40334041
// CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12 // encoding: [0x0c,0x20,0x18,0xd5]
4042+
// CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12 // encoding: [0x0c,0x20,0x1c,0xd5]
40344043
// CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12 // encoding: [0x0c,0x20,0x1e,0xd5]
40354044
// CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12 // encoding: [0x2c,0x20,0x18,0xd5]
40364045
// CHECK: msr {{tcr_el1|TCR_EL1}}, x12 // encoding: [0x4c,0x20,0x18,0xd5]
40374046
// CHECK: msr {{tcr_el2|TCR_EL2}}, x12 // encoding: [0x4c,0x20,0x1c,0xd5]
40384047
// CHECK: msr {{tcr_el3|TCR_EL3}}, x12 // encoding: [0x4c,0x20,0x1e,0xd5]
4048+
// CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12 // encoding: [0x0c,0x21,0x1c,0xd5]
40394049
// CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12 // encoding: [0x4c,0x21,0x1c,0xd5]
40404050
// CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12 // encoding: [0x0c,0x30,0x1c,0xd5]
40414051
// CHECK: msr {{spsr_el1|SPSR_EL1}}, x12 // encoding: [0x0c,0x40,0x18,0xd5]
@@ -4324,11 +4334,13 @@ _func:
43244334
mrs x9, HACR_EL2
43254335
mrs x9, MDCR_EL3
43264336
mrs x9, TTBR0_EL1
4337+
mrs x9, TTBR0_EL2
43274338
mrs x9, TTBR0_EL3
43284339
mrs x9, TTBR1_EL1
43294340
mrs x9, TCR_EL1
43304341
mrs x9, TCR_EL2
43314342
mrs x9, TCR_EL3
4343+
mrs x9, VTTBR_EL2
43324344
mrs x9, VTCR_EL2
43334345
mrs x9, DACR32_EL2
43344346
mrs x9, SPSR_EL1
@@ -4625,11 +4637,13 @@ _func:
46254637
// CHECK: mrs x9, {{hacr_el2|HACR_EL2}} // encoding: [0xe9,0x11,0x3c,0xd5]
46264638
// CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}} // encoding: [0x29,0x13,0x3e,0xd5]
46274639
// CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}} // encoding: [0x09,0x20,0x38,0xd5]
4640+
// CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}} // encoding: [0x09,0x20,0x3c,0xd5]
46284641
// CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}} // encoding: [0x09,0x20,0x3e,0xd5]
46294642
// CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}} // encoding: [0x29,0x20,0x38,0xd5]
46304643
// CHECK: mrs x9, {{tcr_el1|TCR_EL1}} // encoding: [0x49,0x20,0x38,0xd5]
46314644
// CHECK: mrs x9, {{tcr_el2|TCR_EL2}} // encoding: [0x49,0x20,0x3c,0xd5]
46324645
// CHECK: mrs x9, {{tcr_el3|TCR_EL3}} // encoding: [0x49,0x20,0x3e,0xd5]
4646+
// CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}} // encoding: [0x09,0x21,0x3c,0xd5]
46334647
// CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}} // encoding: [0x49,0x21,0x3c,0xd5]
46344648
// CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}} // encoding: [0x09,0x30,0x3c,0xd5]
46354649
// CHECK: mrs x9, {{spsr_el1|SPSR_EL1}} // encoding: [0x09,0x40,0x38,0xd5]

‎llvm/test/MC/Disassembler/AArch64/arm64-branch.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,10 +29,14 @@
2929
# CHECK: dcps1 #0x2
3030
0x62 0x00 0xa0 0xd4
3131
# CHECK: dcps2 #0x3
32+
0x83 0x00 0xa0 0xd4
33+
# CHECK: dcps3 #0x4
3234
0xa0 0x00 0x40 0xd4
3335
# CHECK: hlt #0x5
3436
0xc2 0x00 0x00 0xd4
3537
# CHECK: hvc #0x6
38+
0xe3 0x00 0x00 0xd4
39+
# CHECK: smc #0x7
3640
0x01 0x01 0x00 0xd4
3741
# CHECK: svc #0x8
3842

‎llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt‎

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
2-
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s
3-
# RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
1+
# RUN: llvm-mc -triple=aarch64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s
2+
# RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s
3+
# RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
44
# RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82
55
# RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83
66

@@ -1257,21 +1257,27 @@
12571257
0xe1 0xff 0x1f 0xd4
12581258

12591259
# CHECK: hvc #{{1|0x1}}
1260+
# CHECK: smc #{{12000|0x2ee0}}
12601261
# CHECK: brk #{{12|0xc}}
12611262
# CHECK: hlt #{{123|0x7b}}
12621263
0x22 0x0 0x0 0xd4
1264+
0x3 0xdc 0x5 0xd4
12631265
0x80 0x1 0x20 0xd4
12641266
0x60 0xf 0x40 0xd4
12651267

12661268
# CHECK: dcps1 #{{42|0x2a}}
12671269
# CHECK: dcps2 #{{9|0x9}}
1270+
# CHECK: dcps3 #{{1000|0x3e8}}
12681271
0x41 0x5 0xa0 0xd4
12691272
0x22 0x1 0xa0 0xd4
1273+
0x3 0x7d 0xa0 0xd4
12701274

12711275
# CHECK: dcps1
12721276
# CHECK: dcps2
1277+
# CHECK: dcps3
12731278
0x1 0x0 0xa0 0xd4
12741279
0x2 0x0 0xa0 0xd4
1280+
0x3 0x0 0xa0 0xd4
12751281

12761282
#------------------------------------------------------------------------------
12771283
# Extract (immediate)
@@ -3252,11 +3258,13 @@
32523258
# CHECK: msr {{hacr_el2|HACR_EL2}}, x12
32533259
# CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12
32543260
# CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12
3261+
# CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12
32553262
# CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12
32563263
# CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12
32573264
# CHECK: msr {{tcr_el1|TCR_EL1}}, x12
32583265
# CHECK: msr {{tcr_el2|TCR_EL2}}, x12
32593266
# CHECK: msr {{tcr_el3|TCR_EL3}}, x12
3267+
# CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12
32603268
# CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12
32613269
# CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12
32623270
# CHECK: msr {{spsr_el1|SPSR_EL1}}, x12
@@ -3546,11 +3554,13 @@
35463554
# CHECK: mrs x9, {{hacr_el2|HACR_EL2}}
35473555
# CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}}
35483556
# CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}}
3557+
# CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}}
35493558
# CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}}
35503559
# CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}}
35513560
# CHECK: mrs x9, {{tcr_el1|TCR_EL1}}
35523561
# CHECK: mrs x9, {{tcr_el2|TCR_EL2}}
35533562
# CHECK: mrs x9, {{tcr_el3|TCR_EL3}}
3563+
# CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}}
35543564
# CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}}
35553565
# CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}}
35563566
# CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}

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