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1 parent 0e28fd7 commit c128f3bCopy full SHA for c128f3b
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-int.ll
@@ -840,7 +840,6 @@ define <8 x i32> @shuffle_spread3_singlesrc_e32(<8 x i32> %v) {
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ret <8 x i32> %out
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}
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-; TODO: This should be a single vslideup.vi
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define <8 x i32> @shuffle_spread4_singlesrc_e32(<8 x i32> %v) {
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; CHECK-LABEL: shuffle_spread4_singlesrc_e32:
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; CHECK: # %bb.0:
@@ -937,7 +936,6 @@ define <8 x i32> @shuffle_decompress_singlesrc_e32(<8 x i32> %v) {
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define <8 x i8> @shuffle_decompress_singlesrc_e8(<8 x i8> %v) {
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; CHECK-LABEL: shuffle_decompress_singlesrc_e8:
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