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AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints
This removes special case processing in TargetInstrInfo::getRegClass to fixup register operands which depending on the subtarget support AGPRs, or require even aligned registers. This regresses assembler diagnostics, which currently work by hackily accepting invalid cases and then post-rejecting a validly parsed instruction. On the plus side this now emits a comment when disassembling unaligned registers for targets with the alignment requirement.
1 parent 7c666e2 commit c1ac2e0

31 files changed

+2770
-2606
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPU.td‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2776,6 +2776,9 @@ def HasGetWaveIdInst : Predicate<"Subtarget->hasGetWaveIdInst()">,
27762776
def HasMAIInsts : Predicate<"Subtarget->hasMAIInsts()">,
27772777
AssemblerPredicate<(all_of FeatureMAIInsts)>;
27782778

2779+
def NotHasMAIInsts : Predicate<"!Subtarget->hasMAIInsts()">,
2780+
AssemblerPredicate<(all_of (not FeatureMAIInsts))>;
2781+
27792782
def HasSMemRealTime : Predicate<"Subtarget->hasSMemRealTime()">,
27802783
AssemblerPredicate<(all_of FeatureSMemRealTime)>;
27812784

@@ -2950,6 +2953,20 @@ def HasLdsBarrierArriveAtomic : Predicate<"Subtarget->hasLdsBarrierArriveAtomic(
29502953
def HasSetPrioIncWgInst : Predicate<"Subtarget->hasSetPrioIncWgInst()">,
29512954
AssemblerPredicate<(all_of FeatureSetPrioIncWgInst)>;
29522955

2956+
def NeedsAlignedVGPRs : Predicate<"Subtarget->needsAlignedVGPRs()">,
2957+
AssemblerPredicate<(all_of FeatureRequiresAlignedVGPRs)>;
2958+
2959+
//===----------------------------------------------------------------------===//
2960+
// HwModes
2961+
//===----------------------------------------------------------------------===//
2962+
2963+
// gfx90a-gfx950. Has AGPRs, and also the align2 VGPR/AGPR requirement
2964+
def AVAlign2LoadStoreMode : HwMode<[HasMAIInsts, NeedsAlignedVGPRs]>;
2965+
2966+
// gfx1250, has alignment requirement but no AGPRs.
2967+
def AlignedVGPRNoAGPRMode : HwMode<[NotHasMAIInsts, NeedsAlignedVGPRs]>;
2968+
2969+
29532970
// Include AMDGPU TD files
29542971
include "SISchedule.td"
29552972
include "GCNProcessors.td"

‎llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -393,12 +393,13 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
393393

394394
switch (N->getMachineOpcode()) {
395395
default: {
396-
const MCInstrDesc &Desc =
397-
Subtarget->getInstrInfo()->get(N->getMachineOpcode());
396+
const SIInstrInfo *TII = Subtarget->getInstrInfo();
397+
const MCInstrDesc &Desc = TII->get(N->getMachineOpcode());
398398
unsigned OpIdx = Desc.getNumDefs() + OpNo;
399399
if (OpIdx >= Desc.getNumOperands())
400400
return nullptr;
401-
int RegClass = Desc.operands()[OpIdx].RegClass;
401+
402+
int16_t RegClass = TII->getOpRegClassID(Desc.operands()[OpIdx]);
402403
if (RegClass == -1)
403404
return nullptr;
404405

@@ -4353,7 +4354,8 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
43534354
if (!RC || SIRI->isSGPRClass(RC))
43544355
return false;
43554356

4356-
if (RC != &AMDGPU::VS_32RegClass && RC != &AMDGPU::VS_64RegClass) {
4357+
if (RC != &AMDGPU::VS_32RegClass && RC != &AMDGPU::VS_64RegClass &&
4358+
RC != &AMDGPU::VS_64_Align2RegClass) {
43574359
AllUsesAcceptSReg = false;
43584360
SDNode *User = U->getUser();
43594361
if (User->isMachineOpcode()) {
@@ -4367,7 +4369,8 @@ bool AMDGPUDAGToDAGISel::isVGPRImm(const SDNode * N) const {
43674369
const TargetRegisterClass *CommutedRC =
43684370
getOperandRegClass(U->getUser(), CommutedOpNo);
43694371
if (CommutedRC == &AMDGPU::VS_32RegClass ||
4370-
CommutedRC == &AMDGPU::VS_64RegClass)
4372+
CommutedRC == &AMDGPU::VS_64RegClass ||
4373+
CommutedRC == &AMDGPU::VS_64_Align2RegClass)
43714374
AllUsesAcceptSReg = true;
43724375
}
43734376
}

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1347,6 +1347,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
13471347
bool ForcedDPP = false;
13481348
bool ForcedSDWA = false;
13491349
KernelScopeInfo KernelScope;
1350+
const unsigned HwMode;
13501351

13511352
/// @name Auto-generated Match Functions
13521353
/// {
@@ -1356,6 +1357,13 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
13561357

13571358
/// }
13581359

1360+
/// Get size of register operand
1361+
unsigned getRegOperandSize(const MCInstrDesc &Desc, unsigned OpNo) const {
1362+
assert(OpNo < Desc.NumOperands);
1363+
int16_t RCID = MII.getOpRegClassID(Desc.operands()[OpNo], HwMode);
1364+
return getRegBitWidth(RCID) / 8;
1365+
}
1366+
13591367
private:
13601368
void createConstantSymbol(StringRef Id, int64_t Val);
13611369

@@ -1442,9 +1450,9 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
14421450
using OptionalImmIndexMap = std::map<AMDGPUOperand::ImmTy, unsigned>;
14431451

14441452
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
1445-
const MCInstrInfo &MII,
1446-
const MCTargetOptions &Options)
1447-
: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {
1453+
const MCInstrInfo &MII, const MCTargetOptions &Options)
1454+
: MCTargetAsmParser(Options, STI, MII), Parser(_Parser),
1455+
HwMode(STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)) {
14481456
MCAsmParserExtension::Initialize(Parser);
14491457

14501458
setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
@@ -4106,7 +4114,7 @@ bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst, SMLoc IDLoc) {
41064114
if ((DMaskIdx == -1 || TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray
41074115
return true;
41084116

4109-
unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);
4117+
unsigned VDataSize = getRegOperandSize(Desc, VDataIdx);
41104118
unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;
41114119
unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;
41124120
if (DMask == 0)
@@ -4170,8 +4178,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc) {
41704178
const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
41714179
bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
41724180
unsigned ActualAddrSize =
4173-
IsNSA ? SrsrcIdx - VAddr0Idx
4174-
: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;
4181+
IsNSA ? SrsrcIdx - VAddr0Idx : getRegOperandSize(Desc, VAddr0Idx) / 4;
41754182

41764183
unsigned ExpectedAddrSize =
41774184
AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());
@@ -4181,8 +4188,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst, SMLoc IDLoc) {
41814188
ExpectedAddrSize >
41824189
getNSAMaxSize(Desc.TSFlags & SIInstrFlags::VSAMPLE)) {
41834190
int VAddrLastIdx = SrsrcIdx - 1;
4184-
unsigned VAddrLastSize =
4185-
AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;
4191+
unsigned VAddrLastSize = getRegOperandSize(Desc, VAddrLastIdx) / 4;
41864192

41874193
ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;
41884194
}
@@ -4428,7 +4434,8 @@ bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
44284434
return true;
44294435

44304436
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
4431-
if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)
4437+
if (TRI->getRegClass(MII.getOpRegClassID(Desc.operands()[0], HwMode))
4438+
.getSizeInBits() <= 128)
44324439
return true;
44334440

44344441
if (TRI->regsOverlap(Src2Reg, DstReg)) {
@@ -4999,7 +5006,7 @@ bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
49995006
unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
50005007

50015008
if (!AMDGPU::isLegalDPALU_DPPControl(getSTI(), DppCtrl) &&
5002-
AMDGPU::isDPALU_DPP(MII.get(Opc), getSTI())) {
5009+
AMDGPU::isDPALU_DPP(MII.get(Opc), MII, getSTI())) {
50035010
// DP ALU DPP is supported for row_newbcast only on GFX9* and row_share
50045011
// only on GFX12.
50055012
SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);
@@ -5522,7 +5529,8 @@ bool AMDGPUAsmParser::validateWMMA(const MCInst &Inst,
55225529
unsigned Fmt = Inst.getOperand(FmtIdx).getImm();
55235530
int SrcIdx = AMDGPU::getNamedOperandIdx(Opc, SrcOp);
55245531
unsigned RegSize =
5525-
TRI->getRegClass(Desc.operands()[SrcIdx].RegClass).getSizeInBits();
5532+
TRI->getRegClass(MII.getOpRegClassID(Desc.operands()[SrcIdx], HwMode))
5533+
.getSizeInBits();
55265534

55275535
if (RegSize == AMDGPU::wmmaScaleF8F6F4FormatToNumRegs(Fmt) * 32)
55285536
return true;

‎llvm/lib/Target/AMDGPU/BUFInstructions.td‎

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -417,10 +417,10 @@ class getBUFVDataRegisterOperandForOp<RegisterOperand Op, bit isTFE> {
417417
}
418418

419419
class getMUBUFInsDA<list<RegisterOperand> vdataList,
420-
list<RegisterClass> vaddrList, bit isTFE, bit hasRestrictedSOffset> {
420+
list<RegisterClassLike> vaddrList, bit isTFE, bit hasRestrictedSOffset> {
421421
RegisterOperand vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
422-
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
423-
RegisterOperand vdata_op = getBUFVDataRegisterOperandForOp<vdataClass, isTFE>.ret;
422+
RegisterClassLike vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
423+
RegisterOperand vdata_op = getBUFVDataRegisterOperand<!cast<SIRegisterClassLike>(vdataClass.RegClass).Size, isTFE>.ret;
424424

425425
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
426426
dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz));
@@ -453,8 +453,8 @@ class getMUBUFIns<int addrKind, list<RegisterOperand> vdataList, bit isTFE, bit
453453
!if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList, [], isTFE, hasRestrictedSOffset>.ret,
454454
!if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPR_32], isTFE, hasRestrictedSOffset>.ret,
455455
!if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPR_32], isTFE, hasRestrictedSOffset>.ret,
456-
!if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64], isTFE, hasRestrictedSOffset>.ret,
457-
!if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64], isTFE, hasRestrictedSOffset>.ret,
456+
!if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VReg_64_AlignTarget], isTFE, hasRestrictedSOffset>.ret,
457+
!if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VReg_64_AlignTarget], isTFE, hasRestrictedSOffset>.ret,
458458
(ins))))));
459459
}
460460

@@ -677,8 +677,8 @@ class MUBUF_Pseudo_Store_Lds<string opName>
677677
}
678678

679679
class getMUBUFAtomicInsDA<RegisterOperand vdata_op, bit vdata_in, bit hasRestrictedSOffset,
680-
list<RegisterClass> vaddrList=[]> {
681-
RegisterClass vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
680+
list<RegisterClassLike> vaddrList=[]> {
681+
RegisterClassLike vaddrClass = !if(!empty(vaddrList), ?, !head(vaddrList));
682682

683683
dag VData = !if(vdata_in, (ins vdata_op:$vdata_in), (ins vdata_op:$vdata));
684684
dag Data = !if(!empty(vaddrList), VData, !con(VData, (ins vaddrClass:$vaddr)));
@@ -702,9 +702,9 @@ class getMUBUFAtomicIns<int addrKind,
702702
!if(!eq(addrKind, BUFAddrKind.IdxEn),
703703
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VGPR_32]>.ret,
704704
!if(!eq(addrKind, BUFAddrKind.BothEn),
705-
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64]>.ret,
705+
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64_AlignTarget]>.ret,
706706
!if(!eq(addrKind, BUFAddrKind.Addr64),
707-
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64]>.ret,
707+
getMUBUFAtomicInsDA<vdataClass, vdata_in, hasRestrictedSOffset, [VReg_64_AlignTarget]>.ret,
708708
(ins))))));
709709
}
710710

@@ -1568,11 +1568,12 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15681568
# !if(!eq(RtnMode, "ret"), "", "_noret")
15691569
# "_" # vt);
15701570
defvar InstSuffix = !if(!eq(RtnMode, "ret"), "_RTN", "");
1571-
defvar data_vt_RC = getVregSrcForVT<data_vt>.ret.RegClass;
1571+
defvar data_op = getVregSrcForVT<data_vt>.ret;
1572+
defvar data_vt_RC = getVregClassForVT<data_vt>.ret;
15721573

15731574
let AddedComplexity = !if(!eq(RtnMode, "ret"), 0, 1) in {
15741575
defvar OffsetResDag = (!cast<MUBUF_Pseudo>(Inst # "_OFFSET" # InstSuffix)
1575-
data_vt_RC:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
1576+
data_op:$vdata_in, SReg_128:$srsrc, SCSrc_b32:$soffset,
15761577
Offset:$offset);
15771578
def : GCNPat<
15781579
(vt (Op (MUBUFOffset v4i32:$srsrc, i32:$soffset, i32:$offset), data_vt:$vdata_in)),
@@ -1583,7 +1584,7 @@ multiclass BufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, string
15831584
>;
15841585

15851586
defvar Addr64ResDag = (!cast<MUBUF_Pseudo>(Inst # "_ADDR64" # InstSuffix)
1586-
data_vt_RC:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
1587+
data_op:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc,
15871588
SCSrc_b32:$soffset, Offset:$offset);
15881589
def : GCNPat<
15891590
(vt (Op (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i32:$offset),
@@ -1832,7 +1833,7 @@ multiclass SIBufferAtomicCmpSwapPat_Common<ValueType vt, ValueType data_vt, stri
18321833
(extract_cpol_set_glc $auxiliary),
18331834
(extract_cpol $auxiliary));
18341835
defvar SrcRC = getVregSrcForVT<vt>.ret;
1835-
defvar DataRC = getVregSrcForVT<data_vt>.ret.RegClass;
1836+
defvar DataRC = getVregClassForVT<data_vt>.ret;
18361837
defvar SubLo = !if(!eq(vt, i32), sub0, sub0_sub1);
18371838
defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3);
18381839

@@ -2088,7 +2089,7 @@ defm : MUBUFStore_PatternOffset <"BUFFER_STORE_SHORT", i16, store_global>;
20882089

20892090
multiclass MUBUFScratchStorePat_Common <string Instr,
20902091
ValueType vt, PatFrag st,
2091-
RegisterClass rc = VGPR_32> {
2092+
RegisterClassLike rc = VGPR_32> {
20922093
def : GCNPat <
20932094
(st vt:$value, (MUBUFScratchOffen v4i32:$srsrc, i32:$vaddr,
20942095
i32:$soffset, i32:$offset)),
@@ -2104,7 +2105,7 @@ multiclass MUBUFScratchStorePat_Common <string Instr,
21042105

21052106
multiclass MUBUFScratchStorePat <string Instr,
21062107
ValueType vt, PatFrag st,
2107-
RegisterClass rc = VGPR_32> {
2108+
RegisterClassLike rc = VGPR_32> {
21082109
let SubtargetPredicate = HasUnrestrictedSOffset in {
21092110
defm : MUBUFScratchStorePat_Common<Instr, vt, st, rc>;
21102111
}

‎llvm/lib/Target/AMDGPU/DSInstructions.td‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -904,7 +904,7 @@ let SubtargetPredicate = isGFX1250Plus in {
904904
let WaveSizePredicate = isWave32, mayStore = 0 in {
905905
let OtherPredicates = [HasTransposeLoadF4F6Insts] in {
906906
defm DS_LOAD_TR4_B64 : DS_1A_RET_NoM0<"ds_load_tr4_b64", VGPROp_64>;
907-
defm DS_LOAD_TR6_B96 : DS_1A_RET_NoM0<"ds_load_tr6_b96", VGPROp_96>;
907+
defm DS_LOAD_TR6_B96 : DS_1A_RET_NoM0<"ds_load_tr6_b96", VGPROp_96_Align1>;
908908
} // End OtherPredicates = [HasTransposeLoadF4F6Insts]
909909
defm DS_LOAD_TR8_B64 : DS_1A_RET_NoM0<"ds_load_tr8_b64", VGPROp_64>;
910910
defm DS_LOAD_TR16_B128 : DS_1A_RET_NoM0<"ds_load_tr16_b128", VGPROp_128>;
@@ -934,7 +934,7 @@ let WaveSizePredicate = isWave64, SubtargetPredicate = HasGFX950Insts, mayStore
934934
defm DS_READ_B64_TR_B4 : DS_1A_RET_NoM0<"ds_read_b64_tr_b4", AVLdSt_64>;
935935
defm DS_READ_B64_TR_B8 : DS_1A_RET_NoM0<"ds_read_b64_tr_b8", AVLdSt_64>;
936936
defm DS_READ_B64_TR_B16 : DS_1A_RET_NoM0<"ds_read_b64_tr_b16", AVLdSt_64>;
937-
defm DS_READ_B96_TR_B6 : DS_1A_RET_NoM0<"ds_read_b96_tr_b6", AVLdSt_96>;
937+
defm DS_READ_B96_TR_B6 : DS_1A_RET_NoM0<"ds_read_b96_tr_b6", AVLdSt_96_Align1>;
938938
}
939939

940940
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,9 @@ static int64_t getInlineImmVal64(unsigned Imm);
5757
AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
5858
MCContext &Ctx, MCInstrInfo const *MCII)
5959
: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
60-
MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
60+
MAI(*Ctx.getAsmInfo()),
61+
HwModeRegClass(STI.getHwMode(MCSubtargetInfo::HwMode_RegInfo)),
62+
TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
6163
CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
6264
// ToDo: AMDGPUDisassembler supports only VI ISA.
6365
if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())
@@ -825,7 +827,8 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
825827
}
826828
}
827829

828-
if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) {
830+
const MCInstrDesc &Desc = MCII->get(MI.getOpcode());
831+
if (Desc.TSFlags & SIInstrFlags::MIMG) {
829832
int VAddr0Idx =
830833
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
831834
int RsrcIdx =
@@ -838,7 +841,7 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
838841
for (unsigned i = 0; i < NSAArgs; ++i) {
839842
const unsigned VAddrIdx = VAddr0Idx + 1 + i;
840843
auto VAddrRCID =
841-
MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass;
844+
MCII->getOpRegClassID(Desc.operands()[VAddrIdx], HwModeRegClass);
842845
MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i]));
843846
}
844847
Bytes = Bytes.slice(4 * NSAWords);
@@ -1311,7 +1314,8 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
13111314
// Widen the register to the correct number of enabled channels.
13121315
MCRegister NewVdata;
13131316
if (DstSize != Info->VDataDwords) {
1314-
auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass;
1317+
auto DataRCID = MCII->getOpRegClassID(
1318+
MCII->get(NewOpcode).operands()[VDataIdx], HwModeRegClass);
13151319

13161320
// Get first subregister of VData
13171321
MCRegister Vdata0 = MI.getOperand(VDataIdx).getReg();
@@ -1338,7 +1342,9 @@ void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
13381342
MCRegister VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0);
13391343
VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA;
13401344

1341-
auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass;
1345+
auto AddrRCID = MCII->getOpRegClassID(
1346+
MCII->get(NewOpcode).operands()[VAddrSAIdx], HwModeRegClass);
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const MCRegisterClass &NewRC = MRI.getRegClass(AddrRCID);
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NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, &NewRC);
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NewVAddrSA = CheckVGPROverflow(NewVAddrSA, NewRC, MRI);

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@ class AMDGPUDisassembler : public MCDisassembler {
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std::unique_ptr<MCInstrInfo const> const MCII;
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const MCRegisterInfo &MRI;
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const MCAsmInfo &MAI;
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const unsigned HwModeRegClass;
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const unsigned TargetMaxInstBytes;
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mutable ArrayRef<uint8_t> Bytes;
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mutable uint32_t Literal;

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