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davemgreendavemgreen
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[AArch64] Fix postinc operands for Neoverse-N2 scheduling
Similar to D159254, this fixes the order of WriteAdr operands on post/pre-inc loads/stores in the Neoverse-N2 scheduling model.
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-1976
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‎llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td‎

Lines changed: 51 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -742,7 +742,7 @@ def : SchedAlias<WriteLDIdx, N2Write_4cyc_1I_1L>;
742742
// Load pair, signed immed offset, signed words
743743
def : InstRW<[N2Write_5cyc_1M0, WriteLDHi], (instrs LDPSWi)>;
744744
// Load pair, immed post-index or immed pre-index, signed words
745-
def : InstRW<[N2Write_5cyc_1M0, WriteLDHi, WriteAdr],
745+
def : InstRW<[WriteAdr, N2Write_5cyc_1M0, WriteLDHi],
746746
(instregex "^LDPSW(post|pre)$")>;
747747

748748
// Store instructions
@@ -860,7 +860,7 @@ def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[SDQ]l$",
860860
// Load vector reg, immed post-index
861861
def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
862862
// Load vector reg, immed pre-index
863-
def : InstRW<[N2Write_6cyc_1I_1L, WriteAdr], (instregex "^LDR[BHSDQ]pre$")>;
863+
def : InstRW<[WriteAdr, N2Write_6cyc_1I_1L], (instregex "^LDR[BHSDQ]pre$")>;
864864

865865
// Load vector reg, unsigned immed
866866
def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
@@ -883,12 +883,12 @@ def : InstRW<[N2Write_6cyc_2L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
883883

884884
// Load vector pair, immed post-index, S/D-form
885885
// Load vector pair, immed pre-index, S/D-form
886-
def : InstRW<[N2Write_6cyc_1I_1L, WriteLDHi, WriteAdr],
886+
def : InstRW<[WriteAdr, N2Write_6cyc_1I_1L, WriteLDHi],
887887
(instregex "^LDP[SD](pre|post)$")>;
888888

889889
// Load vector pair, immed post-index, Q-form
890890
// Load vector pair, immed pre-index, Q-form
891-
def : InstRW<[N2Write_6cyc_2I_2L, WriteLDHi, WriteAdr], (instrs LDPQpost,
891+
def : InstRW<[WriteAdr, N2Write_6cyc_2I_2L, WriteLDHi], (instrs LDPQpost,
892892
LDPQpre)>;
893893

894894
// FP store instructions
@@ -1238,223 +1238,223 @@ def : InstRW<[N2Write_5cyc_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
12381238

12391239
// ASIMD load, 1 element, multiple, 1 reg, D-form
12401240
def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1Onev(8b|4h|2s|1d)$")>;
1241-
def : InstRW<[N2Write_6cyc_1L, WriteAdr],
1241+
def : InstRW<[WriteAdr, N2Write_6cyc_1L],
12421242
(instregex "^LD1Onev(8b|4h|2s|1d)_POST$")>;
12431243

12441244
// ASIMD load, 1 element, multiple, 1 reg, Q-form
12451245
def : InstRW<[N2Write_6cyc_1L], (instregex "^LD1Onev(16b|8h|4s|2d)$")>;
1246-
def : InstRW<[N2Write_6cyc_1L, WriteAdr],
1246+
def : InstRW<[WriteAdr, N2Write_6cyc_1L],
12471247
(instregex "^LD1Onev(16b|8h|4s|2d)_POST$")>;
12481248

12491249
// ASIMD load, 1 element, multiple, 2 reg, D-form
12501250
def : InstRW<[N2Write_6cyc_2L], (instregex "^LD1Twov(8b|4h|2s|1d)$")>;
1251-
def : InstRW<[N2Write_6cyc_2L, WriteAdr],
1251+
def : InstRW<[WriteAdr, N2Write_6cyc_2L],
12521252
(instregex "^LD1Twov(8b|4h|2s|1d)_POST$")>;
12531253

12541254
// ASIMD load, 1 element, multiple, 2 reg, Q-form
12551255
def : InstRW<[N2Write_6cyc_2L], (instregex "^LD1Twov(16b|8h|4s|2d)$")>;
1256-
def : InstRW<[N2Write_6cyc_2L, WriteAdr],
1256+
def : InstRW<[WriteAdr, N2Write_6cyc_2L],
12571257
(instregex "^LD1Twov(16b|8h|4s|2d)_POST$")>;
12581258

12591259
// ASIMD load, 1 element, multiple, 3 reg, D-form
12601260
def : InstRW<[N2Write_6cyc_3L], (instregex "^LD1Threev(8b|4h|2s|1d)$")>;
1261-
def : InstRW<[N2Write_6cyc_3L, WriteAdr],
1261+
def : InstRW<[WriteAdr, N2Write_6cyc_3L],
12621262
(instregex "^LD1Threev(8b|4h|2s|1d)_POST$")>;
12631263

12641264
// ASIMD load, 1 element, multiple, 3 reg, Q-form
12651265
def : InstRW<[N2Write_6cyc_3L], (instregex "^LD1Threev(16b|8h|4s|2d)$")>;
1266-
def : InstRW<[N2Write_6cyc_3L, WriteAdr],
1266+
def : InstRW<[WriteAdr, N2Write_6cyc_3L],
12671267
(instregex "^LD1Threev(16b|8h|4s|2d)_POST$")>;
12681268

12691269
// ASIMD load, 1 element, multiple, 4 reg, D-form
12701270
def : InstRW<[N2Write_7cyc_4L], (instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
1271-
def : InstRW<[N2Write_7cyc_4L, WriteAdr],
1271+
def : InstRW<[WriteAdr, N2Write_7cyc_4L],
12721272
(instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
12731273

12741274
// ASIMD load, 1 element, multiple, 4 reg, Q-form
12751275
def : InstRW<[N2Write_7cyc_4L], (instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
1276-
def : InstRW<[N2Write_7cyc_4L, WriteAdr],
1276+
def : InstRW<[WriteAdr, N2Write_7cyc_4L],
12771277
(instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
12781278

12791279
// ASIMD load, 1 element, one lane, B/H/S
12801280
// ASIMD load, 1 element, one lane, D
12811281
def : InstRW<[N2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)$")>;
1282-
def : InstRW<[N2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
1282+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_1V], (instregex "LD1i(8|16|32|64)_POST$")>;
12831283

12841284
// ASIMD load, 1 element, all lanes, D-form, B/H/S
12851285
// ASIMD load, 1 element, all lanes, D-form, D
12861286
def : InstRW<[N2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)$")>;
1287-
def : InstRW<[N2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
1287+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_1V], (instregex "LD1Rv(8b|4h|2s|1d)_POST$")>;
12881288

12891289
// ASIMD load, 1 element, all lanes, Q-form
12901290
def : InstRW<[N2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)$")>;
1291-
def : InstRW<[N2Write_8cyc_1L_1V, WriteAdr], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
1291+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_1V], (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
12921292

12931293
// ASIMD load, 2 element, multiple, D-form, B/H/S
12941294
def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)$")>;
1295-
def : InstRW<[N2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
1295+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2Twov(8b|4h|2s)_POST$")>;
12961296

12971297
// ASIMD load, 2 element, multiple, Q-form, B/H/S
12981298
// ASIMD load, 2 element, multiple, Q-form, D
12991299
def : InstRW<[N2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
1300-
def : InstRW<[N2Write_8cyc_2L_2V, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
1300+
def : InstRW<[WriteAdr, N2Write_8cyc_2L_2V], (instregex "LD2Twov(16b|8h|4s|2d)_POST$")>;
13011301

13021302
// ASIMD load, 2 element, one lane, B/H
13031303
// ASIMD load, 2 element, one lane, S
13041304
// ASIMD load, 2 element, one lane, D
13051305
def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)$")>;
1306-
def : InstRW<[N2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2i(8|16|32|64)_POST$")>;
1306+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2i(8|16|32|64)_POST$")>;
13071307

13081308
// ASIMD load, 2 element, all lanes, D-form, B/H/S
13091309
// ASIMD load, 2 element, all lanes, D-form, D
13101310
def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)$")>;
1311-
def : InstRW<[N2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
1311+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2Rv(8b|4h|2s|1d)_POST$")>;
13121312

13131313
// ASIMD load, 2 element, all lanes, Q-form
13141314
def : InstRW<[N2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)$")>;
1315-
def : InstRW<[N2Write_8cyc_1L_2V, WriteAdr], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
1315+
def : InstRW<[WriteAdr, N2Write_8cyc_1L_2V], (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
13161316

13171317
// ASIMD load, 3 element, multiple, D-form, B/H/S
13181318
def : InstRW<[N2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)$")>;
1319-
def : InstRW<[N2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
1319+
def : InstRW<[WriteAdr, N2Write_8cyc_2L_3V], (instregex "LD3Threev(8b|4h|2s)_POST$")>;
13201320

13211321
// ASIMD load, 3 element, multiple, Q-form, B/H/S
13221322
def : InstRW<[N2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s)$")>;
1323-
def : InstRW<[N2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
1323+
def : InstRW<[WriteAdr, N2Write_8cyc_3L_3V], (instregex "LD3Threev(16b|8h|4s)_POST$")>;
13241324

13251325
// ASIMD load, 3 element, multiple, Q-form, D
13261326
def : InstRW<[N2Write_8cyc_3L_3V], (instregex "LD3Threev(2d)$")>;
1327-
def : InstRW<[N2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Threev(2d)_POST$")>;
1327+
def : InstRW<[WriteAdr, N2Write_8cyc_3L_3V], (instregex "LD3Threev(2d)_POST$")>;
13281328

13291329
// ASIMD load, 3 element, one lane, B/H
13301330
// ASIMD load, 3 element, one lane, S
13311331
// ASIMD load, 3 element, one lane, D
13321332
def : InstRW<[N2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)$")>;
1333-
def : InstRW<[N2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
1333+
def : InstRW<[WriteAdr, N2Write_8cyc_2L_3V], (instregex "LD3i(8|16|32|64)_POST$")>;
13341334

13351335
// ASIMD load, 3 element, all lanes, D-form, B/H/S
13361336
// ASIMD load, 3 element, all lanes, D-form, D
13371337
def : InstRW<[N2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)$")>;
1338-
def : InstRW<[N2Write_8cyc_2L_3V, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
1338+
def : InstRW<[WriteAdr, N2Write_8cyc_2L_3V], (instregex "LD3Rv(8b|4h|2s|1d)_POST$")>;
13391339

13401340
// ASIMD load, 3 element, all lanes, Q-form, B/H/S
13411341
// ASIMD load, 3 element, all lanes, Q-form, D
13421342
def : InstRW<[N2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)$")>;
1343-
def : InstRW<[N2Write_8cyc_3L_3V, WriteAdr], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
1343+
def : InstRW<[WriteAdr, N2Write_8cyc_3L_3V], (instregex "LD3Rv(16b|8h|4s|2d)_POST$")>;
13441344

13451345
// ASIMD load, 4 element, multiple, D-form, B/H/S
13461346
def : InstRW<[N2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)$")>;
1347-
def : InstRW<[N2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
1347+
def : InstRW<[WriteAdr, N2Write_8cyc_3L_4V], (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
13481348

13491349
// ASIMD load, 4 element, multiple, Q-form, B/H/S
13501350
// ASIMD load, 4 element, multiple, Q-form, D
13511351
def : InstRW<[N2Write_9cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
1352-
def : InstRW<[N2Write_9cyc_4L_4V, WriteAdr], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
1352+
def : InstRW<[WriteAdr, N2Write_9cyc_4L_4V], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
13531353

13541354
// ASIMD load, 4 element, one lane, B/H
13551355
// ASIMD load, 4 element, one lane, S
13561356
// ASIMD load, 4 element, one lane, D
13571357
def : InstRW<[N2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)$")>;
1358-
def : InstRW<[N2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
1358+
def : InstRW<[WriteAdr, N2Write_8cyc_3L_4V], (instregex "LD4i(8|16|32|64)_POST$")>;
13591359

13601360
// ASIMD load, 4 element, all lanes, D-form, B/H/S
13611361
// ASIMD load, 4 element, all lanes, D-form, D
13621362
def : InstRW<[N2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)$")>;
1363-
def : InstRW<[N2Write_8cyc_3L_4V, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
1363+
def : InstRW<[WriteAdr, N2Write_8cyc_3L_4V], (instregex "LD4Rv(8b|4h|2s|1d)_POST$")>;
13641364

13651365
// ASIMD load, 4 element, all lanes, Q-form, B/H/S
13661366
// ASIMD load, 4 element, all lanes, Q-form, D
13671367
def : InstRW<[N2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)$")>;
1368-
def : InstRW<[N2Write_8cyc_4L_4V, WriteAdr], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
1368+
def : InstRW<[WriteAdr, N2Write_8cyc_4L_4V], (instregex "LD4Rv(16b|8h|4s|2d)_POST$")>;
13691369

13701370
// ASIMD store instructions
13711371
// -----------------------------------------------------------------------------
13721372

13731373
// ASIMD store, 1 element, multiple, 1 reg, D-form
13741374
def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)$")>;
1375-
def : InstRW<[N2Write_2cyc_1L01_1V, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
1375+
def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V], (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
13761376

13771377
// ASIMD store, 1 element, multiple, 1 reg, Q-form
13781378
def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)$")>;
1379-
def : InstRW<[N2Write_2cyc_1L01_1V, WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
1379+
def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V], (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
13801380

13811381
// ASIMD store, 1 element, multiple, 2 reg, D-form
13821382
def : InstRW<[N2Write_2cyc_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)$")>;
1383-
def : InstRW<[N2Write_2cyc_1L01_1V, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
1383+
def : InstRW<[WriteAdr, N2Write_2cyc_1L01_1V], (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
13841384

13851385
// ASIMD store, 1 element, multiple, 2 reg, Q-form
13861386
def : InstRW<[N2Write_2cyc_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)$")>;
1387-
def : InstRW<[N2Write_2cyc_2L01_2V, WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
1387+
def : InstRW<[WriteAdr, N2Write_2cyc_2L01_2V], (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
13881388

13891389
// ASIMD store, 1 element, multiple, 3 reg, D-form
13901390
def : InstRW<[N2Write_2cyc_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)$")>;
1391-
def : InstRW<[N2Write_2cyc_2L01_2V, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
1391+
def : InstRW<[WriteAdr, N2Write_2cyc_2L01_2V], (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
13921392

13931393
// ASIMD store, 1 element, multiple, 3 reg, Q-form
13941394
def : InstRW<[N2Write_2cyc_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)$")>;
1395-
def : InstRW<[N2Write_2cyc_3L01_3V, WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
1395+
def : InstRW<[WriteAdr, N2Write_2cyc_3L01_3V], (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
13961396

13971397
// ASIMD store, 1 element, multiple, 4 reg, D-form
13981398
def : InstRW<[N2Write_2cyc_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
1399-
def : InstRW<[N2Write_2cyc_2L01_2V, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
1399+
def : InstRW<[WriteAdr, N2Write_2cyc_2L01_2V], (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
14001400

14011401
// ASIMD store, 1 element, multiple, 4 reg, Q-form
14021402
def : InstRW<[N2Write_2cyc_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
1403-
def : InstRW<[N2Write_2cyc_4L01_4V, WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
1403+
def : InstRW<[WriteAdr, N2Write_2cyc_4L01_4V], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
14041404

14051405
// ASIMD store, 1 element, one lane, B/H/S
14061406
// ASIMD store, 1 element, one lane, D
14071407
def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "ST1i(8|16|32|64)$")>;
1408-
def : InstRW<[N2Write_4cyc_1L01_1V, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
1408+
def : InstRW<[WriteAdr, N2Write_4cyc_1L01_1V], (instregex "ST1i(8|16|32|64)_POST$")>;
14091409

14101410
// ASIMD store, 2 element, multiple, D-form, B/H/S
14111411
def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "ST2Twov(8b|4h|2s)$")>;
1412-
def : InstRW<[N2Write_4cyc_1L01_1V, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
1412+
def : InstRW<[WriteAdr, N2Write_4cyc_1L01_1V], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
14131413

14141414
// ASIMD store, 2 element, multiple, Q-form, B/H/S
14151415
// ASIMD store, 2 element, multiple, Q-form, D
14161416
def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
1417-
def : InstRW<[N2Write_4cyc_2L01_2V, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
1417+
def : InstRW<[WriteAdr, N2Write_4cyc_2L01_2V], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
14181418

14191419
// ASIMD store, 2 element, one lane, B/H/S
14201420
// ASIMD store, 2 element, one lane, D
14211421
def : InstRW<[N2Write_4cyc_1L01_1V], (instregex "ST2i(8|16|32|64)$")>;
1422-
def : InstRW<[N2Write_4cyc_1L01_1V, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
1422+
def : InstRW<[WriteAdr, N2Write_4cyc_1L01_1V], (instregex "ST2i(8|16|32|64)_POST$")>;
14231423

14241424
// ASIMD store, 3 element, multiple, D-form, B/H/S
14251425
def : InstRW<[N2Write_5cyc_2L01_2V], (instregex "ST3Threev(8b|4h|2s)$")>;
1426-
def : InstRW<[N2Write_5cyc_2L01_2V, WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
1426+
def : InstRW<[WriteAdr, N2Write_5cyc_2L01_2V], (instregex "ST3Threev(8b|4h|2s)_POST$")>;
14271427

14281428
// ASIMD store, 3 element, multiple, Q-form, B/H/S
14291429
// ASIMD store, 3 element, multiple, Q-form, D
14301430
def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)$")>;
1431-
def : InstRW<[N2Write_6cyc_3L01_3V, WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
1431+
def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST3Threev(16b|8h|4s|2d)_POST$")>;
14321432

14331433
// ASIMD store, 3 element, one lane, B/H
14341434
// ASIMD store, 3 element, one lane, S
14351435
// ASIMD store, 3 element, one lane, D
14361436
def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST3i(8|16|32|64)$")>;
1437-
def : InstRW<[N2Write_6cyc_3L01_3V, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
1437+
def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST3i(8|16|32|64)_POST$")>;
14381438

14391439
// ASIMD store, 4 element, multiple, D-form, B/H/S
14401440
def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)$")>;
1441-
def : InstRW<[N2Write_6cyc_3L01_3V, WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
1441+
def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
14421442

14431443
// ASIMD store, 4 element, multiple, Q-form, B/H/S
14441444
def : InstRW<[N2Write_7cyc_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)$")>;
1445-
def : InstRW<[N2Write_7cyc_6L01_6V, WriteAdr], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
1445+
def : InstRW<[WriteAdr, N2Write_7cyc_6L01_6V], (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
14461446

14471447
// ASIMD store, 4 element, multiple, Q-form, D
14481448
def : InstRW<[N2Write_5cyc_4L01_4V], (instregex "ST4Fourv(2d)$")>;
1449-
def : InstRW<[N2Write_5cyc_4L01_4V, WriteAdr], (instregex "ST4Fourv(2d)_POST$")>;
1449+
def : InstRW<[WriteAdr, N2Write_5cyc_4L01_4V], (instregex "ST4Fourv(2d)_POST$")>;
14501450

14511451
// ASIMD store, 4 element, one lane, B/H/S
14521452
def : InstRW<[N2Write_6cyc_3L01_3V], (instregex "ST4i(8|16|32)$")>;
1453-
def : InstRW<[N2Write_6cyc_3L01_3V, WriteAdr], (instregex "ST4i(8|16|32)_POST$")>;
1453+
def : InstRW<[WriteAdr, N2Write_6cyc_3L01_3V], (instregex "ST4i(8|16|32)_POST$")>;
14541454

14551455
// ASIMD store, 4 element, one lane, D
14561456
def : InstRW<[N2Write_4cyc_3L01_3V], (instregex "ST4i(64)$")>;
1457-
def : InstRW<[N2Write_4cyc_3L01_3V, WriteAdr], (instregex "ST4i(64)_POST$")>;
1457+
def : InstRW<[WriteAdr, N2Write_4cyc_3L01_3V], (instregex "ST4i(64)_POST$")>;
14581458

14591459
// Cryptography extensions
14601460
// -----------------------------------------------------------------------------

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