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[RFC][TableGen] Require DAG argument for complex operands in InstAlias
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12 files changed

+327
-314
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12 files changed

+327
-314
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 59 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -3027,8 +3027,12 @@ class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
30273027

30283028
// Aliases for register+register add/subtract.
30293029
class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
3030-
RegisterClass src1Regtype, RegisterClass src2Regtype,
3031-
int shiftExt>
3030+
RegisterClass src1Regtype, dag src2>
3031+
: InstAlias<asm#"\t$dst, $src1, $src2",
3032+
(inst dstRegtype:$dst, src1Regtype:$src1, src2)>;
3033+
class AddSubRegAlias64<string asm, Instruction inst, RegisterClass dstRegtype,
3034+
RegisterClass src1Regtype, RegisterClass src2Regtype,
3035+
int shiftExt>
30323036
: InstAlias<asm#"\t$dst, $src1, $src2",
30333037
(inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
30343038
shiftExt)>;
@@ -3096,22 +3100,22 @@ multiclass AddSub<bit isSub, string mnemonic, string alias,
30963100

30973101
// Register/register aliases with no shift when SP is not used.
30983102
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3099-
GPR32, GPR32, GPR32, 0>;
3103+
GPR32, GPR32, (arith_shifted_reg32 GPR32:$src2, 0)>;
31003104
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3101-
GPR64, GPR64, GPR64, 0>;
3105+
GPR64, GPR64, (arith_shifted_reg64 GPR64:$src2, 0)>;
31023106

31033107
// Register/register aliases with no shift when either the destination or
31043108
// first source register is SP.
31053109
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
3106-
GPR32sponly, GPR32sp, GPR32, 16>; // UXTW #0
3110+
GPR32sponly, GPR32sp,
3111+
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
31073112
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
3108-
GPR32sp, GPR32sponly, GPR32, 16>; // UXTW #0
3109-
def : AddSubRegAlias<mnemonic,
3110-
!cast<Instruction>(NAME#"Xrx64"),
3111-
GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
3112-
def : AddSubRegAlias<mnemonic,
3113-
!cast<Instruction>(NAME#"Xrx64"),
3114-
GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
3113+
GPR32sp, GPR32sponly,
3114+
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
3115+
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
3116+
GPR64sponly, GPR64sp, GPR64, 24>; // UXTX #0
3117+
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
3118+
GPR64sp, GPR64sponly, GPR64, 24>; // UXTX #0
31153119
}
31163120

31173121
multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
@@ -3175,15 +3179,19 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
31753179
def : InstAlias<cmp#"\t$src, $imm", (!cast<Instruction>(NAME#"Xri")
31763180
XZR, GPR64sp:$src, addsub_shifted_imm64:$imm), 5>;
31773181
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrx")
3178-
WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
3182+
WZR, GPR32sp:$src1,
3183+
(arith_extended_reg32_i32 GPR32:$src2, arith_extend:$sh)), 4>;
31793184
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx")
3180-
XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh), 4>;
3185+
XZR, GPR64sp:$src1,
3186+
(arith_extended_reg32_i64 GPR32:$src2, arith_extend:$sh)), 4>;
31813187
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrx64")
31823188
XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh), 4>;
31833189
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Wrs")
3184-
WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh), 4>;
3190+
WZR, GPR32:$src1,
3191+
(arith_shifted_reg32 GPR32:$src2, arith_shift32:$sh)), 4>;
31853192
def : InstAlias<cmp#"\t$src1, $src2$sh", (!cast<Instruction>(NAME#"Xrs")
3186-
XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh), 4>;
3193+
XZR, GPR64:$src1,
3194+
(arith_shifted_reg64 GPR64:$src2, arith_shift64:$sh)), 4>;
31873195

31883196
// Support negative immediates, e.g. cmp Rn, -imm -> cmn Rn, imm
31893197
def : InstSubst<cmpAlias#"\t$src, $imm", (!cast<Instruction>(NAME#"Wri")
@@ -3193,27 +3201,28 @@ multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp,
31933201

31943202
// Compare shorthands
31953203
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrs")
3196-
WZR, GPR32:$src1, GPR32:$src2, 0), 5>;
3204+
WZR, GPR32:$src1, (arith_shifted_reg32 GPR32:$src2, 0)), 5>;
31973205
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrs")
3198-
XZR, GPR64:$src1, GPR64:$src2, 0), 5>;
3206+
XZR, GPR64:$src1, (arith_shifted_reg64 GPR64:$src2, 0)), 5>;
31993207
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Wrx")
3200-
WZR, GPR32sponly:$src1, GPR32:$src2, 16), 5>;
3208+
WZR, GPR32sponly:$src1,
3209+
(arith_extended_reg32_i32 GPR32:$src2, 16)), 5>;
32013210
def : InstAlias<cmp#"\t$src1, $src2", (!cast<Instruction>(NAME#"Xrx64")
32023211
XZR, GPR64sponly:$src1, GPR64:$src2, 24), 5>;
32033212

32043213
// Register/register aliases with no shift when SP is not used.
32053214
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3206-
GPR32, GPR32, GPR32, 0>;
3215+
GPR32, GPR32, (arith_shifted_reg32 GPR32:$src2, 0)>;
32073216
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3208-
GPR64, GPR64, GPR64, 0>;
3217+
GPR64, GPR64, (arith_shifted_reg64 GPR64:$src2, 0)>;
32093218

32103219
// Register/register aliases with no shift when the first source register
32113220
// is SP.
32123221
def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
3213-
GPR32, GPR32sponly, GPR32, 16>; // UXTW #0
3214-
def : AddSubRegAlias<mnemonic,
3215-
!cast<Instruction>(NAME#"Xrx64"),
3216-
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
3222+
GPR32, GPR32sponly,
3223+
(arith_extended_reg32_i32 GPR32:$src2, 16)>; // UXTW #0
3224+
def : AddSubRegAlias64<mnemonic, !cast<Instruction>(NAME#"Xrx64"),
3225+
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
32173226
}
32183227

32193228
class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
@@ -3398,9 +3407,10 @@ class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
33983407
}
33993408

34003409
// Aliases for register+register logical instructions.
3401-
class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
3410+
class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype,
3411+
dag op2>
34023412
: InstAlias<asm#"\t$dst, $src1, $src2",
3403-
(inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
3413+
(inst regtype:$dst, regtype:$src1, op2)>;
34043414

34053415
multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode,
34063416
string Alias> {
@@ -3472,10 +3482,10 @@ multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
34723482
let Inst{31} = 1;
34733483
}
34743484

3475-
def : LogicalRegAlias<mnemonic,
3476-
!cast<Instruction>(NAME#"Wrs"), GPR32>;
3477-
def : LogicalRegAlias<mnemonic,
3478-
!cast<Instruction>(NAME#"Xrs"), GPR64>;
3485+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3486+
GPR32, (logical_shifted_reg32 GPR32:$src2, 0)>;
3487+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3488+
GPR64, (logical_shifted_reg64 GPR64:$src2, 0)>;
34793489
}
34803490

34813491
// Split from LogicalReg to allow setting NZCV Defs
@@ -3495,10 +3505,10 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
34953505
}
34963506
} // Defs = [NZCV]
34973507

3498-
def : LogicalRegAlias<mnemonic,
3499-
!cast<Instruction>(NAME#"Wrs"), GPR32>;
3500-
def : LogicalRegAlias<mnemonic,
3501-
!cast<Instruction>(NAME#"Xrs"), GPR64>;
3508+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
3509+
GPR32, (logical_shifted_reg32 GPR32:$src2, 0)>;
3510+
def : LogicalRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
3511+
GPR64, (logical_shifted_reg64 GPR64:$src2, 0)>;
35023512
}
35033513

35043514
//---
@@ -3986,9 +3996,10 @@ class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
39863996
let Inst{4-0} = Rt;
39873997
}
39883998

3989-
class ROInstAlias<string asm, DAGOperand regtype, Instruction INST>
3999+
class ROInstAlias<string asm, DAGOperand regtype, Instruction INST,
4000+
ro_extend ext>
39904001
: InstAlias<asm # "\t$Rt, [$Rn, $Rm]",
3991-
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
4002+
(INST regtype:$Rt, GPR64sp:$Rn, GPR64:$Rm, (ext 0, 0))>;
39924003

39934004
multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
39944005
string asm, ValueType Ty, SDPatternOperator loadop> {
@@ -4014,7 +4025,7 @@ multiclass Load8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
40144025
let Inst{13} = 0b1;
40154026
}
40164027

4017-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4028+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend8>;
40184029
}
40194030

40204031
multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4039,7 +4050,7 @@ multiclass Store8RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
40394050
let Inst{13} = 0b1;
40404051
}
40414052

4042-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4053+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend8>;
40434054
}
40444055

40454056
class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4086,7 +4097,7 @@ multiclass Load16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
40864097
let Inst{13} = 0b1;
40874098
}
40884099

4089-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4100+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend16>;
40904101
}
40914102

40924103
multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4111,7 +4122,7 @@ multiclass Store16RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
41114122
let Inst{13} = 0b1;
41124123
}
41134124

4114-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4125+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend16>;
41154126
}
41164127

41174128
class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4158,7 +4169,7 @@ multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
41584169
let Inst{13} = 0b1;
41594170
}
41604171

4161-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4172+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend32>;
41624173
}
41634174

41644175
multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4183,7 +4194,7 @@ multiclass Store32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
41834194
let Inst{13} = 0b1;
41844195
}
41854196

4186-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4197+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend32>;
41874198
}
41884199

41894200
class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4230,7 +4241,7 @@ multiclass Load64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
42304241
let Inst{13} = 0b1;
42314242
}
42324243

4233-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4244+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
42344245
}
42354246

42364247
multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4255,7 +4266,7 @@ multiclass Store64RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
42554266
let Inst{13} = 0b1;
42564267
}
42574268

4258-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4269+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
42594270
}
42604271

42614272
class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
@@ -4302,7 +4313,7 @@ multiclass Load128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
43024313
let Inst{13} = 0b1;
43034314
}
43044315

4305-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4316+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend128>;
43064317
}
43074318

43084319
multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
@@ -4323,7 +4334,7 @@ multiclass Store128RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
43234334
let Inst{13} = 0b1;
43244335
}
43254336

4326-
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
4337+
def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX"), ro_Xextend128>;
43274338
}
43284339

43294340
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
@@ -4372,9 +4383,7 @@ multiclass PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm> {
43724383
let Inst{13} = 0b1;
43734384
}
43744385

4375-
def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
4376-
(!cast<Instruction>(NAME # "roX") prfop:$Rt,
4377-
GPR64sp:$Rn, GPR64:$Rm, 0, 0)>;
4386+
def : ROInstAlias<"prfm", prfop, !cast<Instruction>(NAME # "roX"), ro_Xextend64>;
43784387
}
43794388

43804389
//---

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 54 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -2636,13 +2636,17 @@ defm ADD : AddSub<0, "add", "sub", add>;
26362636
defm SUB : AddSub<1, "sub", "add">;
26372637

26382638
def : InstAlias<"mov $dst, $src",
2639-
(ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
2639+
(ADDWri GPR32sponly:$dst, GPR32sp:$src,
2640+
(addsub_shifted_imm32 0, 0))>;
26402641
def : InstAlias<"mov $dst, $src",
2641-
(ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
2642+
(ADDWri GPR32sp:$dst, GPR32sponly:$src,
2643+
(addsub_shifted_imm32 0, 0))>;
26422644
def : InstAlias<"mov $dst, $src",
2643-
(ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
2645+
(ADDXri GPR64sponly:$dst, GPR64sp:$src,
2646+
(addsub_shifted_imm64 0, 0))>;
26442647
def : InstAlias<"mov $dst, $src",
2645-
(ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
2648+
(ADDXri GPR64sp:$dst, GPR64sponly:$src,
2649+
(addsub_shifted_imm64 0, 0))>;
26462650

26472651
defm ADDS : AddSubS<0, "adds", AArch64add_flag, "cmn", "subs", "cmp">;
26482652
defm SUBS : AddSubS<1, "subs", AArch64sub_flag, "cmp", "adds", "cmn">;
@@ -2702,19 +2706,31 @@ def : Pat<(AArch64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
27022706
(ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
27032707
}
27042708

2705-
def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
2706-
def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
2709+
def : InstAlias<"neg $dst, $src",
2710+
(SUBWrs GPR32:$dst, WZR,
2711+
(arith_shifted_reg32 GPR32:$src, 0)), 3>;
2712+
def : InstAlias<"neg $dst, $src",
2713+
(SUBXrs GPR64:$dst, XZR,
2714+
(arith_shifted_reg64 GPR64:$src, 0)), 3>;
27072715
def : InstAlias<"neg $dst, $src$shift",
2708-
(SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
2716+
(SUBWrs GPR32:$dst, WZR,
2717+
(arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;
27092718
def : InstAlias<"neg $dst, $src$shift",
2710-
(SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
2711-
2712-
def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0), 3>;
2713-
def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0), 3>;
2719+
(SUBXrs GPR64:$dst, XZR,
2720+
(arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;
2721+
2722+
def : InstAlias<"negs $dst, $src",
2723+
(SUBSWrs GPR32:$dst, WZR,
2724+
(arith_shifted_reg32 GPR32:$src, 0)), 3>;
2725+
def : InstAlias<"negs $dst, $src",
2726+
(SUBSXrs GPR64:$dst, XZR,
2727+
(arith_shifted_reg64 GPR64:$src, 0)), 3>;
27142728
def : InstAlias<"negs $dst, $src$shift",
2715-
(SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift), 2>;
2729+
(SUBSWrs GPR32:$dst, WZR,
2730+
(arith_shifted_reg32 GPR32:$src, arith_shift32:$shift)), 2>;
27162731
def : InstAlias<"negs $dst, $src$shift",
2717-
(SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift), 2>;
2732+
(SUBSXrs GPR64:$dst, XZR,
2733+
(arith_shifted_reg64 GPR64:$src, arith_shift64:$shift)), 2>;
27182734

27192735

27202736
// Unsigned/Signed divide
@@ -3141,31 +3157,45 @@ defm ORN : LogicalReg<0b01, 1, "orn",
31413157
BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
31423158
defm ORR : LogicalReg<0b01, 0, "orr", or>;
31433159

3144-
def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0), 2>;
3145-
def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0), 2>;
3146-
3147-
def : InstAlias<"mvn $Wd, $Wm", (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0), 3>;
3148-
def : InstAlias<"mvn $Xd, $Xm", (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0), 3>;
3160+
def : InstAlias<"mov $dst, $src",
3161+
(ORRWrs GPR32:$dst, WZR,
3162+
(logical_shifted_reg32 GPR32:$src, 0)), 2>;
3163+
def : InstAlias<"mov $dst, $src",
3164+
(ORRXrs GPR64:$dst, XZR,
3165+
(logical_shifted_reg64 GPR64:$src, 0)), 2>;
3166+
3167+
def : InstAlias<"mvn $Wd, $Wm",
3168+
(ORNWrs GPR32:$Wd, WZR,
3169+
(logical_shifted_reg32 GPR32:$Wm, 0)), 3>;
3170+
def : InstAlias<"mvn $Xd, $Xm",
3171+
(ORNXrs GPR64:$Xd, XZR,
3172+
(logical_shifted_reg64 GPR64:$Xm, 0)), 3>;
31493173

31503174
def : InstAlias<"mvn $Wd, $Wm$sh",
3151-
(ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh), 2>;
3175+
(ORNWrs GPR32:$Wd, WZR,
3176+
(logical_shifted_reg32 GPR32:$Wm, logical_shift32:$sh)), 2>;
31523177
def : InstAlias<"mvn $Xd, $Xm$sh",
3153-
(ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh), 2>;
3178+
(ORNXrs GPR64:$Xd, XZR,
3179+
(logical_shifted_reg64 GPR64:$Xm, logical_shift64:$sh)), 2>;
31543180

31553181
def : InstAlias<"tst $src1, $src2",
31563182
(ANDSWri WZR, GPR32:$src1, logical_imm32:$src2), 2>;
31573183
def : InstAlias<"tst $src1, $src2",
31583184
(ANDSXri XZR, GPR64:$src1, logical_imm64:$src2), 2>;
31593185

31603186
def : InstAlias<"tst $src1, $src2",
3161-
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0), 3>;
3187+
(ANDSWrs WZR, GPR32:$src1,
3188+
(logical_shifted_reg32 GPR32:$src2, 0)), 3>;
31623189
def : InstAlias<"tst $src1, $src2",
3163-
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0), 3>;
3190+
(ANDSXrs XZR, GPR64:$src1,
3191+
(logical_shifted_reg64 GPR64:$src2, 0)), 3>;
31643192

31653193
def : InstAlias<"tst $src1, $src2$sh",
3166-
(ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh), 2>;
3194+
(ANDSWrs WZR, GPR32:$src1,
3195+
(logical_shifted_reg32 GPR32:$src2, logical_shift32:$sh)), 2>;
31673196
def : InstAlias<"tst $src1, $src2$sh",
3168-
(ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh), 2>;
3197+
(ANDSXrs XZR, GPR64:$src1,
3198+
(logical_shifted_reg64 GPR64:$src2, logical_shift64:$sh)), 2>;
31693199

31703200

31713201
def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;

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