fix vmsge

jacquesguan · jacquesguan · commit c1eb4101ff6b · 2024-11-13T11:02:33.000+08:00
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1632,7 +1632,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
             break;
           IsCmpMinimum = true;
         } else if (!IsUnsigned && CVal == APInt::getSignedMinValue(
-                                              Src1VT.getScalarSizeInBits())) {
+                                              Src1VT.getScalarSizeInBits())
+                                              .getSExtValue()) {
           IsCmpMinimum = true;
         }
       }
@@ -1708,7 +1709,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
             break;
           IsCmpMinimum = true;
         } else if (!IsUnsigned && CVal == APInt::getSignedMinValue(
-                                              Src1VT.getScalarSizeInBits())) {
+                                              Src1VT.getScalarSizeInBits())
+                                              .getSExtValue()) {
           IsCmpMinimum = true;
         }
       }

Original file line number	Diff line number	Diff line change
`@@ -1632,7 +1632,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {`
`1632`	`1632`	`break;`
`1633`	`1633`	`IsCmpMinimum = true;`
`1634`	`1634`	`} else if (!IsUnsigned && CVal == APInt::getSignedMinValue(`
`1635`		`- Src1VT.getScalarSizeInBits())) {`
	`1635`	`+ Src1VT.getScalarSizeInBits())`
	`1636`	`+ .getSExtValue()) {`
`1636`	`1637`	`IsCmpMinimum = true;`
`1637`	`1638`	`}`
`1638`	`1639`	`}`
`@@ -1708,7 +1709,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {`
`1708`	`1709`	`break;`
`1709`	`1710`	`IsCmpMinimum = true;`
`1710`	`1711`	`} else if (!IsUnsigned && CVal == APInt::getSignedMinValue(`
`1711`		`- Src1VT.getScalarSizeInBits())) {`
	`1712`	`+ Src1VT.getScalarSizeInBits())`
	`1713`	`+ .getSExtValue()) {`
`1712`	`1714`	`IsCmpMinimum = true;`
`1713`	`1715`	`}`
`1714`	`1716`	`}`