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[RISCV] Promote fldexp with Zfh.
The default expansion tries to create i16 operations after type legalization. Fixes #117349
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4 files changed

+228
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -498,7 +498,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
498498
setOperationAction({ISD::FREM, ISD::FPOW, ISD::FPOWI,
499499
ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP,
500500
ISD::FEXP2, ISD::FEXP10, ISD::FLOG, ISD::FLOG2,
501-
ISD::FLOG10},
501+
ISD::FLOG10, ISD::FLDEXP},
502502
MVT::f16, Promote);
503503

504504
// FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have

‎llvm/test/CodeGen/RISCV/double-intrinsics.ll‎

Lines changed: 53 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1637,3 +1637,56 @@ define double @minimumnum_double(double %x, double %y) {
16371637
%z = call double @llvm.minimumnum.f64(double %x, double %y)
16381638
ret double %z
16391639
}
1640+
1641+
define double @ldexp_double(double %x, i32 signext %y) nounwind {
1642+
; RV32IFD-LABEL: ldexp_double:
1643+
; RV32IFD: # %bb.0:
1644+
; RV32IFD-NEXT: tail ldexp
1645+
;
1646+
; RV64IFD-LABEL: ldexp_double:
1647+
; RV64IFD: # %bb.0:
1648+
; RV64IFD-NEXT: addi sp, sp, -16
1649+
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1650+
; RV64IFD-NEXT: call ldexp
1651+
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1652+
; RV64IFD-NEXT: addi sp, sp, 16
1653+
; RV64IFD-NEXT: ret
1654+
;
1655+
; RV32IZFINXZDINX-LABEL: ldexp_double:
1656+
; RV32IZFINXZDINX: # %bb.0:
1657+
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
1658+
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1659+
; RV32IZFINXZDINX-NEXT: call ldexp
1660+
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1661+
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
1662+
; RV32IZFINXZDINX-NEXT: ret
1663+
;
1664+
; RV64IZFINXZDINX-LABEL: ldexp_double:
1665+
; RV64IZFINXZDINX: # %bb.0:
1666+
; RV64IZFINXZDINX-NEXT: addi sp, sp, -16
1667+
; RV64IZFINXZDINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1668+
; RV64IZFINXZDINX-NEXT: call ldexp
1669+
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1670+
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
1671+
; RV64IZFINXZDINX-NEXT: ret
1672+
;
1673+
; RV32I-LABEL: ldexp_double:
1674+
; RV32I: # %bb.0:
1675+
; RV32I-NEXT: addi sp, sp, -16
1676+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1677+
; RV32I-NEXT: call ldexp
1678+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1679+
; RV32I-NEXT: addi sp, sp, 16
1680+
; RV32I-NEXT: ret
1681+
;
1682+
; RV64I-LABEL: ldexp_double:
1683+
; RV64I: # %bb.0:
1684+
; RV64I-NEXT: addi sp, sp, -16
1685+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1686+
; RV64I-NEXT: call ldexp
1687+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1688+
; RV64I-NEXT: addi sp, sp, 16
1689+
; RV64I-NEXT: ret
1690+
%z = call double @llvm.ldexp.f64.i32(double %x, i32 %y)
1691+
ret double %z
1692+
}

‎llvm/test/CodeGen/RISCV/float-intrinsics.ll‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2242,3 +2242,51 @@ define float @minimumnum_float(float %x, float %y) {
22422242
%z = call float @llvm.minimumnum.f32(float %x, float %y)
22432243
ret float %z
22442244
}
2245+
2246+
define float @ldexp_float(float %x, i32 signext %y) nounwind {
2247+
; RV32IF-LABEL: ldexp_float:
2248+
; RV32IF: # %bb.0:
2249+
; RV32IF-NEXT: tail ldexpf
2250+
;
2251+
; RV32IZFINX-LABEL: ldexp_float:
2252+
; RV32IZFINX: # %bb.0:
2253+
; RV32IZFINX-NEXT: tail ldexpf
2254+
;
2255+
; RV64IF-LABEL: ldexp_float:
2256+
; RV64IF: # %bb.0:
2257+
; RV64IF-NEXT: addi sp, sp, -16
2258+
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2259+
; RV64IF-NEXT: call ldexpf
2260+
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2261+
; RV64IF-NEXT: addi sp, sp, 16
2262+
; RV64IF-NEXT: ret
2263+
;
2264+
; RV64IZFINX-LABEL: ldexp_float:
2265+
; RV64IZFINX: # %bb.0:
2266+
; RV64IZFINX-NEXT: addi sp, sp, -16
2267+
; RV64IZFINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2268+
; RV64IZFINX-NEXT: call ldexpf
2269+
; RV64IZFINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2270+
; RV64IZFINX-NEXT: addi sp, sp, 16
2271+
; RV64IZFINX-NEXT: ret
2272+
;
2273+
; RV32I-LABEL: ldexp_float:
2274+
; RV32I: # %bb.0:
2275+
; RV32I-NEXT: addi sp, sp, -16
2276+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
2277+
; RV32I-NEXT: call ldexpf
2278+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
2279+
; RV32I-NEXT: addi sp, sp, 16
2280+
; RV32I-NEXT: ret
2281+
;
2282+
; RV64I-LABEL: ldexp_float:
2283+
; RV64I: # %bb.0:
2284+
; RV64I-NEXT: addi sp, sp, -16
2285+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
2286+
; RV64I-NEXT: call ldexpf
2287+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
2288+
; RV64I-NEXT: addi sp, sp, 16
2289+
; RV64I-NEXT: ret
2290+
%z = call float @llvm.ldexp.f32.i32(float %x, i32 %y)
2291+
ret float %z
2292+
}

‎llvm/test/CodeGen/RISCV/half-intrinsics.ll‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3186,3 +3186,129 @@ define half @minimumnum_half(half %x, half %y) {
31863186
%z = call half @llvm.minimumnum.f16(half %x, half %y)
31873187
ret half %z
31883188
}
3189+
3190+
define half @ldexp_half(half %x, i32 signext %y) nounwind {
3191+
; RV32IZFH-LABEL: ldexp_half:
3192+
; RV32IZFH: # %bb.0:
3193+
; RV32IZFH-NEXT: addi sp, sp, -16
3194+
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3195+
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
3196+
; RV32IZFH-NEXT: call ldexpf
3197+
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
3198+
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3199+
; RV32IZFH-NEXT: addi sp, sp, 16
3200+
; RV32IZFH-NEXT: ret
3201+
;
3202+
; RV64IZFH-LABEL: ldexp_half:
3203+
; RV64IZFH: # %bb.0:
3204+
; RV64IZFH-NEXT: addi sp, sp, -16
3205+
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3206+
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
3207+
; RV64IZFH-NEXT: call ldexpf
3208+
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
3209+
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3210+
; RV64IZFH-NEXT: addi sp, sp, 16
3211+
; RV64IZFH-NEXT: ret
3212+
;
3213+
; RV32IZHINX-LABEL: ldexp_half:
3214+
; RV32IZHINX: # %bb.0:
3215+
; RV32IZHINX-NEXT: addi sp, sp, -16
3216+
; RV32IZHINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3217+
; RV32IZHINX-NEXT: fcvt.s.h a0, a0
3218+
; RV32IZHINX-NEXT: call ldexpf
3219+
; RV32IZHINX-NEXT: fcvt.h.s a0, a0
3220+
; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3221+
; RV32IZHINX-NEXT: addi sp, sp, 16
3222+
; RV32IZHINX-NEXT: ret
3223+
;
3224+
; RV64IZHINX-LABEL: ldexp_half:
3225+
; RV64IZHINX: # %bb.0:
3226+
; RV64IZHINX-NEXT: addi sp, sp, -16
3227+
; RV64IZHINX-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3228+
; RV64IZHINX-NEXT: fcvt.s.h a0, a0
3229+
; RV64IZHINX-NEXT: call ldexpf
3230+
; RV64IZHINX-NEXT: fcvt.h.s a0, a0
3231+
; RV64IZHINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3232+
; RV64IZHINX-NEXT: addi sp, sp, 16
3233+
; RV64IZHINX-NEXT: ret
3234+
;
3235+
; RV32I-LABEL: ldexp_half:
3236+
; RV32I: # %bb.0:
3237+
; RV32I-NEXT: addi sp, sp, -16
3238+
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3239+
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
3240+
; RV32I-NEXT: mv s0, a1
3241+
; RV32I-NEXT: slli a0, a0, 16
3242+
; RV32I-NEXT: srli a0, a0, 16
3243+
; RV32I-NEXT: call __extendhfsf2
3244+
; RV32I-NEXT: mv a1, s0
3245+
; RV32I-NEXT: call ldexpf
3246+
; RV32I-NEXT: call __truncsfhf2
3247+
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3248+
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
3249+
; RV32I-NEXT: addi sp, sp, 16
3250+
; RV32I-NEXT: ret
3251+
;
3252+
; RV64I-LABEL: ldexp_half:
3253+
; RV64I: # %bb.0:
3254+
; RV64I-NEXT: addi sp, sp, -16
3255+
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3256+
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
3257+
; RV64I-NEXT: mv s0, a1
3258+
; RV64I-NEXT: slli a0, a0, 48
3259+
; RV64I-NEXT: srli a0, a0, 48
3260+
; RV64I-NEXT: call __extendhfsf2
3261+
; RV64I-NEXT: mv a1, s0
3262+
; RV64I-NEXT: call ldexpf
3263+
; RV64I-NEXT: call __truncsfhf2
3264+
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3265+
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
3266+
; RV64I-NEXT: addi sp, sp, 16
3267+
; RV64I-NEXT: ret
3268+
;
3269+
; RV32IZFHMIN-LABEL: ldexp_half:
3270+
; RV32IZFHMIN: # %bb.0:
3271+
; RV32IZFHMIN-NEXT: addi sp, sp, -16
3272+
; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3273+
; RV32IZFHMIN-NEXT: fcvt.s.h fa0, fa0
3274+
; RV32IZFHMIN-NEXT: call ldexpf
3275+
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa0
3276+
; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3277+
; RV32IZFHMIN-NEXT: addi sp, sp, 16
3278+
; RV32IZFHMIN-NEXT: ret
3279+
;
3280+
; RV64IZFHMIN-LABEL: ldexp_half:
3281+
; RV64IZFHMIN: # %bb.0:
3282+
; RV64IZFHMIN-NEXT: addi sp, sp, -16
3283+
; RV64IZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3284+
; RV64IZFHMIN-NEXT: fcvt.s.h fa0, fa0
3285+
; RV64IZFHMIN-NEXT: call ldexpf
3286+
; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa0
3287+
; RV64IZFHMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3288+
; RV64IZFHMIN-NEXT: addi sp, sp, 16
3289+
; RV64IZFHMIN-NEXT: ret
3290+
;
3291+
; RV32IZHINXMIN-LABEL: ldexp_half:
3292+
; RV32IZHINXMIN: # %bb.0:
3293+
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
3294+
; RV32IZHINXMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
3295+
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
3296+
; RV32IZHINXMIN-NEXT: call ldexpf
3297+
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
3298+
; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
3299+
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
3300+
; RV32IZHINXMIN-NEXT: ret
3301+
;
3302+
; RV64IZHINXMIN-LABEL: ldexp_half:
3303+
; RV64IZHINXMIN: # %bb.0:
3304+
; RV64IZHINXMIN-NEXT: addi sp, sp, -16
3305+
; RV64IZHINXMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
3306+
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
3307+
; RV64IZHINXMIN-NEXT: call ldexpf
3308+
; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
3309+
; RV64IZHINXMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
3310+
; RV64IZHINXMIN-NEXT: addi sp, sp, 16
3311+
; RV64IZHINXMIN-NEXT: ret
3312+
%z = call half @llvm.ldexp.f16.i32(half %x, i32 %y)
3313+
ret half %z
3314+
}

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