Update with main & Address code review comments

Author: AmrDeveloper

clang/include/clang/CIR/Dialect/IR/CIROps.td

@@ -2217,7 +2217,7 @@ def VecTernaryOp : CIR_Op<"vec.ternary",
   }];
 
   let arguments = (ins
-    IntegerVector:$cond,
+    CIR_VectorOfIntType:$cond,
     CIR_VectorType:$vec1,
     CIR_VectorType:$vec2
   );

clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp

@@ -208,26 +208,30 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> {
     Expr *lhsExpr = e->getTrueExpr();
     Expr *rhsExpr = e->getFalseExpr();
 
+    QualType condType = condExpr->getType();
+
     // OpenCL: If the condition is a vector, we can treat this condition like
     // the select function.
-    if ((cgf.getLangOpts().OpenCL && condExpr->getType()->isVectorType()) ||
-        condExpr->getType()->isExtVectorType()) {
-      cgf.getCIRGenModule().errorNYI(loc,
-                                     "TernaryOp OpenCL VectorType condition");
+    if ((cgf.getLangOpts().OpenCL && condType->isVectorType()) ||
+        condType->isExtVectorType()) {
+      cgf.cgm.errorNYI(loc, "TernaryOp OpenCL VectorType condition");
       return {};
     }
 
-    if (condExpr->getType()->isVectorType() ||
-        condExpr->getType()->isSveVLSBuiltinType()) {
-      assert(condExpr->getType()->isVectorType() && "?: op for SVE vector NYI");
+    if (condType->isVectorType() || condType->isSveVLSBuiltinType()) {
+      if (!condExpr->getType()->isVectorType()) {
+        cgf.cgm.errorNYI(loc, "TernaryOp for SVE vector");
+        return {};
+      }
+
       mlir::Value condValue = Visit(condExpr);
       mlir::Value lhsValue = Visit(lhsExpr);
       mlir::Value rhsValue = Visit(rhsExpr);
       return builder.create<cir::VecTernaryOp>(loc, condValue, lhsValue,
                                                rhsValue);
     }
 
-    cgf.getCIRGenModule().errorNYI(loc, "TernaryOp for non vector types");
+    cgf.cgm.errorNYI(loc, "TernaryOp for non vector types");
     return {};
   }
 

clang/lib/CIR/Dialect/IR/CIRDialect.cpp

@@ -1598,8 +1598,7 @@ LogicalResult cir::VecTernaryOp::verify() {
   // other operands.  (The automatic verification already checked that all
   // operands are vector types and that the second and third operands are the
   // same type.)
-  if (mlir::cast<cir::VectorType>(getCond().getType()).getSize() !=
-      getVec1().getType().getSize()) {
+  if (getCond().getType().getSize() != getVec1().getType().getSize()) {
     return emitOpError() << ": the number of elements in "
                          << getCond().getType() << " and "
                          << getVec1().getType() << " don't match";

clang/test/CIR/CodeGen/vector-ext.cpp

@@ -1091,18 +1091,3 @@ void foo17() {
 // OGCG: %[[VEC_A:.*]] = alloca <2 x double>, align 16
 // OGCG: %[[TMP:.*]] = load <2 x double>, ptr %[[VEC_A]], align 16
 // OGCG: %[[RES:.*]]= fptoui <2 x double> %[[TMP]] to <2 x i16>
-
-void foo20() {
-  vi4 a;
-  vi4 b;
-  vi4 c;
-  vi4 r = c ? a : b;
-}
-
-// CIR: %[[RES:.*]] = cir.vec.ternary({{.*}}, {{.*}}, {{.*}}) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>
-
-// LLVM: %[[VEC_COND:.*]] = icmp ne <4 x i32> {{.*}}, zeroinitializer
-// LLVM: %[[RES:.*]] = select <4 x i1> %[[VEC_COND]], <4 x i32> {{.*}}, <4 x i32> {{.*}}
-
-// OGCG: %[[VEC_COND:.*]] = icmp ne <4 x i32> {{.*}}, zeroinitializer
-// OGCG: %[[RES:.*]] = select <4 x i1> %[[VEC_COND]], <4 x i32> {{.*}}, <4 x i32> {{.*}}