Port existing TargetSchedule flags to ScheduleDAG

Change-Id: I2c7080bce7fadbb7b6c471457edbc0606c1b0bb0

Author: jrbyrnes

llvm/include/llvm/CodeGen/TargetSchedule.h

@@ -45,7 +45,8 @@ class TargetSchedModel {
 
   unsigned computeInstrLatency(const MCSchedClassDesc &SCDesc) const;
 
-  bool DisableItinerariesAndSchedModel = false;
+  bool EnableSchedModel = true;
+  bool EnableSchedItins = true;
 
 public:
   TargetSchedModel() : SchedModel(MCSchedModel::Default) {}
@@ -56,7 +57,7 @@ class TargetSchedModel {
   /// indices and may query TargetSubtargetInfo and TargetInstrInfo to resolve
   /// dynamic properties.
   void init(const TargetSubtargetInfo *TSInfo,
-            bool DisableItinerariesAndSchedModel = false);
+            bool EnableSModel = true, bool EnableSItins = true);
 
   /// Return the MCSchedClassDesc for this instruction.
   const MCSchedClassDesc *resolveSchedClass(const MachineInstr *MI) const;

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

@@ -69,9 +69,11 @@ static cl::opt<bool>
 static cl::opt<bool> UseTBAA("use-tbaa-in-sched-mi", cl::Hidden,
     cl::init(true), cl::desc("Enable use of TBAA during MI DAG construction"));
 
-static cl::opt<bool> DisableSchedModel(
-    "disable-schedmodel-in-sched-mi", cl::Hidden, cl::init(false),
-    cl::desc("Enable use of TBAA during MI DAG construction"));
+static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
+  cl::desc("Use TargetSchedModel for latency lookup"));
+
+static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
+  cl::desc("Use InstrItineraryData for latency lookup"));
 
 // Note: the two options below might be used in tuning compile time vs
 // output quality. Setting HugeRegion so large that it will never be
@@ -125,7 +127,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
   DbgValues.clear();
 
   const TargetSubtargetInfo &ST = mf.getSubtarget();
-  SchedModel.init(&ST, DisableSchedModel);
+  SchedModel.init(&ST, EnableSchedModel, EnableSchedItins);
 }
 
 /// If this machine instr has memory reference information and it can be

llvm/lib/CodeGen/TargetSchedule.cpp

@@ -29,33 +29,26 @@
 
 using namespace llvm;
 
-static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
-  cl::desc("Use TargetSchedModel for latency lookup"));
-
-static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
-  cl::desc("Use InstrItineraryData for latency lookup"));
-
 static cl::opt<bool> ForceEnableIntervals(
     "sched-model-force-enable-intervals", cl::Hidden, cl::init(false),
     cl::desc("Force the use of resource intervals in the schedule model"));
 
 bool TargetSchedModel::hasInstrSchedModel() const {
-  return EnableSchedModel && SchedModel.hasInstrSchedModel() &&
-         !DisableItinerariesAndSchedModel;
+  return EnableSchedModel && SchedModel.hasInstrSchedModel();
 }
 
 bool TargetSchedModel::hasInstrItineraries() const {
-  return EnableSchedItins && !InstrItins.isEmpty() &&
-         !DisableItinerariesAndSchedModel;
+  return EnableSchedItins && !InstrItins.isEmpty();
 }
 
-void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo, bool Disable) {
+void TargetSchedModel::init(const TargetSubtargetInfo *TSInfo, bool EnableSModel, bool EnableSItins) {
   STI = TSInfo;
   SchedModel = TSInfo->getSchedModel();
   TII = TSInfo->getInstrInfo();
   STI->initInstrItins(InstrItins);
 
-  DisableItinerariesAndSchedModel = Disable;
+  EnableSchedModel = EnableSModel;
+  EnableSchedItins = EnableSItins;
 
   unsigned NumRes = SchedModel.getNumProcResourceKinds();
   ResourceFactors.resize(NumRes);

llvm/test/CodeGen/AMDGPU/mai-hazards-gfx942.mir

@@ -1,6 +1,6 @@
 # RUN: llc -mtriple=amdgcn -mcpu=gfx942 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,GFX942 %s
 # RUN: llc -mtriple=amdgcn -mcpu=gfx950 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,GFX950 %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx950 -verify-machineinstrs -run-pass post-RA-hazard-rec --disable-schedmodel-in-sched-mi=1 %s -o - | FileCheck -check-prefixes=GCN,GFX950 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx950 -verify-machineinstrs -run-pass post-RA-hazard-rec --schedmodel=0 %s -o - | FileCheck -check-prefixes=GCN,GFX950 %s
 
 # GCN-LABEL: name: valu_write_vgpr_sgemm_mfma_read
 # GCN:      V_MOV_B32

llvm/test/CodeGen/AMDGPU/sched-no-schedmodel.mir

@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -misched-cluster=false --misched-prera-direction=topdown -run-pass=machine-scheduler --disable-schedmodel-in-sched-mi=0 -o - %s | FileCheck -check-prefix=GCN %s
-# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -misched-cluster=false --misched-prera-direction=topdown -run-pass=machine-scheduler --disable-schedmodel-in-sched-mi=1 -o - %s | FileCheck -check-prefix=GCN-NO-SCHEDMODEL %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -misched-cluster=false --misched-prera-direction=topdown -run-pass=machine-scheduler --schedmodel=1 -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -misched-cluster=false --misched-prera-direction=topdown -run-pass=machine-scheduler --schedmodel=0 -o - %s | FileCheck -check-prefix=GCN-NO-SCHEDMODEL %s
 
 ---
 name: sched_group_barrier_1_VMEM_READ_1_VALU_5_MFMA_1_VMEM_READ_3_VALU_2_VMEM_WRITE