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lenarylenary
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Correctly mark Stack Object as for a Spill
1 parent fffa624 commit c27f1b0

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2 files changed

+49
-49
lines changed

2 files changed

+49
-49
lines changed

‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,7 @@ createSiFivePreemptibleInterruptFrameEntries(MachineFunction &MF,
306306
// objects we might have for X8 and X9, as they might be saved twice.
307307
for (int I = 0; I < 2; ++I) {
308308
int FI = MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC),
309-
false);
309+
true);
310310
RVFI.pushInterruptCSRFrameIndex(FI);
311311
}
312312
}

‎llvm/test/CodeGen/RISCV/sifive-interrupt-attr.ll‎

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -78,16 +78,16 @@ define void @preemptible_empty() "interrupt"="SiFive-CLIC-preemptible" {
7878
; RV32: # %bb.0:
7979
; RV32-NEXT: addi sp, sp, -16
8080
; RV32-NEXT: .cfi_def_cfa_offset 16
81-
; RV32-NEXT: sw s0, 12(sp)
82-
; RV32-NEXT: sw s1, 8(sp)
81+
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
82+
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
8383
; RV32-NEXT: csrr s0, mcause
8484
; RV32-NEXT: csrr s1, mepc
8585
; RV32-NEXT: csrsi mstatus, 8
8686
; RV32-NEXT: csrci mstatus, 8
8787
; RV32-NEXT: csrw mepc, s1
8888
; RV32-NEXT: csrw mcause, s0
89-
; RV32-NEXT: lw s1, 8(sp)
90-
; RV32-NEXT: lw s0, 12(sp)
89+
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
90+
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
9191
; RV32-NEXT: addi sp, sp, 16
9292
; RV32-NEXT: .cfi_def_cfa_offset 0
9393
; RV32-NEXT: mret
@@ -96,16 +96,16 @@ define void @preemptible_empty() "interrupt"="SiFive-CLIC-preemptible" {
9696
; RV64: # %bb.0:
9797
; RV64-NEXT: addi sp, sp, -16
9898
; RV64-NEXT: .cfi_def_cfa_offset 16
99-
; RV64-NEXT: sd s0, 8(sp)
100-
; RV64-NEXT: sd s1, 0(sp)
99+
; RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
100+
; RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
101101
; RV64-NEXT: csrr s0, mcause
102102
; RV64-NEXT: csrr s1, mepc
103103
; RV64-NEXT: csrsi mstatus, 8
104104
; RV64-NEXT: csrci mstatus, 8
105105
; RV64-NEXT: csrw mepc, s1
106106
; RV64-NEXT: csrw mcause, s0
107-
; RV64-NEXT: ld s1, 0(sp)
108-
; RV64-NEXT: ld s0, 8(sp)
107+
; RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
108+
; RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
109109
; RV64-NEXT: addi sp, sp, 16
110110
; RV64-NEXT: .cfi_def_cfa_offset 0
111111
; RV64-NEXT: mret
@@ -118,16 +118,16 @@ define void @both_empty() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
118118
; RV32-NEXT: csrrw sp, mscratchcsw, sp
119119
; RV32-NEXT: addi sp, sp, -16
120120
; RV32-NEXT: .cfi_def_cfa_offset 16
121-
; RV32-NEXT: sw s0, 12(sp)
122-
; RV32-NEXT: sw s1, 8(sp)
121+
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
122+
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
123123
; RV32-NEXT: csrr s0, mcause
124124
; RV32-NEXT: csrr s1, mepc
125125
; RV32-NEXT: csrsi mstatus, 8
126126
; RV32-NEXT: csrci mstatus, 8
127127
; RV32-NEXT: csrw mepc, s1
128128
; RV32-NEXT: csrw mcause, s0
129-
; RV32-NEXT: lw s1, 8(sp)
130-
; RV32-NEXT: lw s0, 12(sp)
129+
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
130+
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
131131
; RV32-NEXT: addi sp, sp, 16
132132
; RV32-NEXT: .cfi_def_cfa_offset 0
133133
; RV32-NEXT: csrrw sp, mscratchcsw, sp
@@ -138,16 +138,16 @@ define void @both_empty() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
138138
; RV64-NEXT: csrrw sp, mscratchcsw, sp
139139
; RV64-NEXT: addi sp, sp, -16
140140
; RV64-NEXT: .cfi_def_cfa_offset 16
141-
; RV64-NEXT: sd s0, 8(sp)
142-
; RV64-NEXT: sd s1, 0(sp)
141+
; RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
142+
; RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
143143
; RV64-NEXT: csrr s0, mcause
144144
; RV64-NEXT: csrr s1, mepc
145145
; RV64-NEXT: csrsi mstatus, 8
146146
; RV64-NEXT: csrci mstatus, 8
147147
; RV64-NEXT: csrw mepc, s1
148148
; RV64-NEXT: csrw mcause, s0
149-
; RV64-NEXT: ld s1, 0(sp)
150-
; RV64-NEXT: ld s0, 8(sp)
149+
; RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
150+
; RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
151151
; RV64-NEXT: addi sp, sp, 16
152152
; RV64-NEXT: .cfi_def_cfa_offset 0
153153
; RV64-NEXT: csrrw sp, mscratchcsw, sp
@@ -484,8 +484,8 @@ define void @preeemptible_caller() "interrupt"="SiFive-CLIC-preemptible" {
484484
; RV32: # %bb.0:
485485
; RV32-NEXT: addi sp, sp, -80
486486
; RV32-NEXT: .cfi_def_cfa_offset 80
487-
; RV32-NEXT: sw s0, 12(sp)
488-
; RV32-NEXT: sw s1, 8(sp)
487+
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
488+
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
489489
; RV32-NEXT: csrr s0, mcause
490490
; RV32-NEXT: csrr s1, mepc
491491
; RV32-NEXT: csrsi mstatus, 8
@@ -557,8 +557,8 @@ define void @preeemptible_caller() "interrupt"="SiFive-CLIC-preemptible" {
557557
; RV32-NEXT: csrci mstatus, 8
558558
; RV32-NEXT: csrw mepc, s1
559559
; RV32-NEXT: csrw mcause, s0
560-
; RV32-NEXT: lw s1, 8(sp)
561-
; RV32-NEXT: lw s0, 12(sp)
560+
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
561+
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
562562
; RV32-NEXT: addi sp, sp, 80
563563
; RV32-NEXT: .cfi_def_cfa_offset 0
564564
; RV32-NEXT: mret
@@ -567,8 +567,8 @@ define void @preeemptible_caller() "interrupt"="SiFive-CLIC-preemptible" {
567567
; RV64: # %bb.0:
568568
; RV64-NEXT: addi sp, sp, -144
569569
; RV64-NEXT: .cfi_def_cfa_offset 144
570-
; RV64-NEXT: sd s0, 8(sp)
571-
; RV64-NEXT: sd s1, 0(sp)
570+
; RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
571+
; RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
572572
; RV64-NEXT: csrr s0, mcause
573573
; RV64-NEXT: csrr s1, mepc
574574
; RV64-NEXT: csrsi mstatus, 8
@@ -640,8 +640,8 @@ define void @preeemptible_caller() "interrupt"="SiFive-CLIC-preemptible" {
640640
; RV64-NEXT: csrci mstatus, 8
641641
; RV64-NEXT: csrw mepc, s1
642642
; RV64-NEXT: csrw mcause, s0
643-
; RV64-NEXT: ld s1, 0(sp)
644-
; RV64-NEXT: ld s0, 8(sp)
643+
; RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
644+
; RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
645645
; RV64-NEXT: addi sp, sp, 144
646646
; RV64-NEXT: .cfi_def_cfa_offset 0
647647
; RV64-NEXT: mret
@@ -655,8 +655,8 @@ define void @both_caller() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
655655
; RV32-NEXT: csrrw sp, mscratchcsw, sp
656656
; RV32-NEXT: addi sp, sp, -80
657657
; RV32-NEXT: .cfi_def_cfa_offset 80
658-
; RV32-NEXT: sw s0, 12(sp)
659-
; RV32-NEXT: sw s1, 8(sp)
658+
; RV32-NEXT: sw s0, 12(sp) # 4-byte Folded Spill
659+
; RV32-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
660660
; RV32-NEXT: csrr s0, mcause
661661
; RV32-NEXT: csrr s1, mepc
662662
; RV32-NEXT: csrsi mstatus, 8
@@ -728,8 +728,8 @@ define void @both_caller() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
728728
; RV32-NEXT: csrci mstatus, 8
729729
; RV32-NEXT: csrw mepc, s1
730730
; RV32-NEXT: csrw mcause, s0
731-
; RV32-NEXT: lw s1, 8(sp)
732-
; RV32-NEXT: lw s0, 12(sp)
731+
; RV32-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
732+
; RV32-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
733733
; RV32-NEXT: addi sp, sp, 80
734734
; RV32-NEXT: .cfi_def_cfa_offset 0
735735
; RV32-NEXT: csrrw sp, mscratchcsw, sp
@@ -740,8 +740,8 @@ define void @both_caller() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
740740
; RV64-NEXT: csrrw sp, mscratchcsw, sp
741741
; RV64-NEXT: addi sp, sp, -144
742742
; RV64-NEXT: .cfi_def_cfa_offset 144
743-
; RV64-NEXT: sd s0, 8(sp)
744-
; RV64-NEXT: sd s1, 0(sp)
743+
; RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
744+
; RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
745745
; RV64-NEXT: csrr s0, mcause
746746
; RV64-NEXT: csrr s1, mepc
747747
; RV64-NEXT: csrsi mstatus, 8
@@ -813,8 +813,8 @@ define void @both_caller() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
813813
; RV64-NEXT: csrci mstatus, 8
814814
; RV64-NEXT: csrw mepc, s1
815815
; RV64-NEXT: csrw mcause, s0
816-
; RV64-NEXT: ld s1, 0(sp)
817-
; RV64-NEXT: ld s0, 8(sp)
816+
; RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
817+
; RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
818818
; RV64-NEXT: addi sp, sp, 144
819819
; RV64-NEXT: .cfi_def_cfa_offset 0
820820
; RV64-NEXT: csrrw sp, mscratchcsw, sp
@@ -930,8 +930,8 @@ define void @preemptible_clobber() "interrupt"="SiFive-CLIC-preemptible" {
930930
; RV32: # %bb.0:
931931
; RV32-NEXT: addi sp, sp, -16
932932
; RV32-NEXT: .cfi_def_cfa_offset 16
933-
; RV32-NEXT: sw s0, 4(sp)
934-
; RV32-NEXT: sw s1, 0(sp)
933+
; RV32-NEXT: sw s0, 4(sp) # 4-byte Folded Spill
934+
; RV32-NEXT: sw s1, 0(sp) # 4-byte Folded Spill
935935
; RV32-NEXT: csrr s0, mcause
936936
; RV32-NEXT: csrr s1, mepc
937937
; RV32-NEXT: csrsi mstatus, 8
@@ -948,8 +948,8 @@ define void @preemptible_clobber() "interrupt"="SiFive-CLIC-preemptible" {
948948
; RV32-NEXT: csrci mstatus, 8
949949
; RV32-NEXT: csrw mepc, s1
950950
; RV32-NEXT: csrw mcause, s0
951-
; RV32-NEXT: lw s1, 0(sp)
952-
; RV32-NEXT: lw s0, 4(sp)
951+
; RV32-NEXT: lw s1, 0(sp) # 4-byte Folded Reload
952+
; RV32-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
953953
; RV32-NEXT: addi sp, sp, 16
954954
; RV32-NEXT: .cfi_def_cfa_offset 0
955955
; RV32-NEXT: mret
@@ -958,8 +958,8 @@ define void @preemptible_clobber() "interrupt"="SiFive-CLIC-preemptible" {
958958
; RV64: # %bb.0:
959959
; RV64-NEXT: addi sp, sp, -32
960960
; RV64-NEXT: .cfi_def_cfa_offset 32
961-
; RV64-NEXT: sd s0, 8(sp)
962-
; RV64-NEXT: sd s1, 0(sp)
961+
; RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
962+
; RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
963963
; RV64-NEXT: csrr s0, mcause
964964
; RV64-NEXT: csrr s1, mepc
965965
; RV64-NEXT: csrsi mstatus, 8
@@ -976,8 +976,8 @@ define void @preemptible_clobber() "interrupt"="SiFive-CLIC-preemptible" {
976976
; RV64-NEXT: csrci mstatus, 8
977977
; RV64-NEXT: csrw mepc, s1
978978
; RV64-NEXT: csrw mcause, s0
979-
; RV64-NEXT: ld s1, 0(sp)
980-
; RV64-NEXT: ld s0, 8(sp)
979+
; RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
980+
; RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
981981
; RV64-NEXT: addi sp, sp, 32
982982
; RV64-NEXT: .cfi_def_cfa_offset 0
983983
; RV64-NEXT: mret
@@ -991,8 +991,8 @@ define void @both_clobber() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
991991
; RV32-NEXT: csrrw sp, mscratchcsw, sp
992992
; RV32-NEXT: addi sp, sp, -16
993993
; RV32-NEXT: .cfi_def_cfa_offset 16
994-
; RV32-NEXT: sw s0, 4(sp)
995-
; RV32-NEXT: sw s1, 0(sp)
994+
; RV32-NEXT: sw s0, 4(sp) # 4-byte Folded Spill
995+
; RV32-NEXT: sw s1, 0(sp) # 4-byte Folded Spill
996996
; RV32-NEXT: csrr s0, mcause
997997
; RV32-NEXT: csrr s1, mepc
998998
; RV32-NEXT: csrsi mstatus, 8
@@ -1009,8 +1009,8 @@ define void @both_clobber() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
10091009
; RV32-NEXT: csrci mstatus, 8
10101010
; RV32-NEXT: csrw mepc, s1
10111011
; RV32-NEXT: csrw mcause, s0
1012-
; RV32-NEXT: lw s1, 0(sp)
1013-
; RV32-NEXT: lw s0, 4(sp)
1012+
; RV32-NEXT: lw s1, 0(sp) # 4-byte Folded Reload
1013+
; RV32-NEXT: lw s0, 4(sp) # 4-byte Folded Reload
10141014
; RV32-NEXT: addi sp, sp, 16
10151015
; RV32-NEXT: .cfi_def_cfa_offset 0
10161016
; RV32-NEXT: csrrw sp, mscratchcsw, sp
@@ -1021,8 +1021,8 @@ define void @both_clobber() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
10211021
; RV64-NEXT: csrrw sp, mscratchcsw, sp
10221022
; RV64-NEXT: addi sp, sp, -32
10231023
; RV64-NEXT: .cfi_def_cfa_offset 32
1024-
; RV64-NEXT: sd s0, 8(sp)
1025-
; RV64-NEXT: sd s1, 0(sp)
1024+
; RV64-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
1025+
; RV64-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
10261026
; RV64-NEXT: csrr s0, mcause
10271027
; RV64-NEXT: csrr s1, mepc
10281028
; RV64-NEXT: csrsi mstatus, 8
@@ -1039,8 +1039,8 @@ define void @both_clobber() "interrupt"="SiFive-CLIC-preemptible-stack-swap" {
10391039
; RV64-NEXT: csrci mstatus, 8
10401040
; RV64-NEXT: csrw mepc, s1
10411041
; RV64-NEXT: csrw mcause, s0
1042-
; RV64-NEXT: ld s1, 0(sp)
1043-
; RV64-NEXT: ld s0, 8(sp)
1042+
; RV64-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
1043+
; RV64-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
10441044
; RV64-NEXT: addi sp, sp, 32
10451045
; RV64-NEXT: .cfi_def_cfa_offset 0
10461046
; RV64-NEXT: csrrw sp, mscratchcsw, sp

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