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[IR] Introduce T<address space> to DataLayout to represent flat address space if a target supports it
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clang/lib/Basic/Targets/AMDGPU.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,7 @@ static const char *const DataLayoutStringAMDGCN =
3636
"-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:"
3737
"32-v48:64-v96:128"
3838
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1"
39-
"-ni:7:8:9";
39+
"-ni:7:8:9-U0";
4040

4141
const LangASMap AMDGPUTargetInfo::AMDGPUDefIsGenMap = {
4242
llvm::AMDGPUAS::FLAT_ADDRESS, // Default

clang/lib/Basic/Targets/NVPTX.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -66,12 +66,12 @@ NVPTXTargetInfo::NVPTXTargetInfo(const llvm::Triple &Triple,
6666
HasFloat16 = true;
6767

6868
if (TargetPointerWidth == 32)
69-
resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
69+
resetDataLayout("e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64-T0");
7070
else if (Opts.NVPTXUseShortPointers)
71-
resetDataLayout(
72-
"e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64");
71+
resetDataLayout("e-p3:32:32-p4:32:32-p5:32:32-i64:64-i128:128-v16:16-v32:"
72+
"32-n16:32:64-U0");
7373
else
74-
resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64");
74+
resetDataLayout("e-i64:64-i128:128-v16:16-v32:32-n16:32:64-U0");
7575

7676
// If possible, get a TargetInfo for our host triple, so we can match its
7777
// types.

clang/test/CodeGen/target-data.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -160,11 +160,11 @@
160160

161161
// RUN: %clang_cc1 -triple nvptx-unknown -o - -emit-llvm %s | \
162162
// RUN: FileCheck %s -check-prefix=NVPTX
163-
// NVPTX: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64"
163+
// NVPTX: target datalayout = "e-p:32:32-i64:64-i128:128-v16:16-v32:32-n16:32:64-U0"
164164

165165
// RUN: %clang_cc1 -triple nvptx64-unknown -o - -emit-llvm %s | \
166166
// RUN: FileCheck %s -check-prefix=NVPTX64
167-
// NVPTX64: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64"
167+
// NVPTX64: target datalayout = "e-i64:64-i128:128-v16:16-v32:32-n16:32:64-U0"
168168

169169
// RUN: %clang_cc1 -triple r600-unknown -o - -emit-llvm %s | \
170170
// RUN: FileCheck %s -check-prefix=R600
@@ -176,12 +176,12 @@
176176

177177
// RUN: %clang_cc1 -triple amdgcn-unknown -target-cpu hawaii -o - -emit-llvm %s \
178178
// RUN: | FileCheck %s -check-prefix=R600SI
179-
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
179+
// R600SI: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-U0"
180180

181181
// Test default -target-cpu
182182
// RUN: %clang_cc1 -triple amdgcn-unknown -o - -emit-llvm %s \
183183
// RUN: | FileCheck %s -check-prefix=R600SIDefault
184-
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
184+
// R600SIDefault: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-U0"
185185

186186
// RUN: %clang_cc1 -triple arm64-unknown -o - -emit-llvm %s | \
187187
// RUN: FileCheck %s -check-prefix=AARCH64
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// RUN: %clang_cc1 %s -O0 -triple amdgcn -emit-llvm -o - | FileCheck %s
22
// RUN: %clang_cc1 %s -O0 -triple amdgcn---opencl -emit-llvm -o - | FileCheck %s
33

4-
// CHECK: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9"
4+
// CHECK: target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-p7:160:256:256:32-p8:128:128-p9:192:256:256:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7:8:9-U0"
55
void foo(void) {}

lld/test/ELF/lto/amdgcn-oses.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525

2626
;--- amdhsa.ll
2727
target triple = "amdgcn-amd-amdhsa"
28-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
28+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-U0"
2929

3030
!llvm.module.flags = !{!0}
3131
!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}
@@ -36,15 +36,15 @@ define void @_start() {
3636

3737
;--- amdpal.ll
3838
target triple = "amdgcn-amd-amdpal"
39-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
39+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-U0"
4040

4141
define amdgpu_cs void @_start() {
4242
ret void
4343
}
4444

4545
;--- mesa3d.ll
4646
target triple = "amdgcn-amd-mesa3d"
47-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
47+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-U0"
4848

4949
define void @_start() {
5050
ret void

lld/test/ELF/lto/amdgcn.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
; Make sure the amdgcn triple is handled
66

77
target triple = "amdgcn-amd-amdhsa"
8-
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
8+
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-U0"
99

1010
define void @_start() {
1111
ret void

llvm/docs/LangRef.rst

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Original file line numberDiff line numberDiff line change
@@ -3076,6 +3076,12 @@ as follows:
30763076
address space 0, this property only affects the default value to be used
30773077
when creating globals without additional contextual information (e.g. in
30783078
LLVM passes).
3079+
``U<address space>``
3080+
Specifies the undesirable address space for a target. This specification does
3081+
not define a new address space; it must correspond to a valid, existing address
3082+
space and be capable of lossless conversion to other address spaces. If this
3083+
specification is absent, it indicates that the target does not have such an
3084+
address space.
30793085

30803086
.. _alloca_addrspace:
30813087

llvm/docs/ReleaseNotes.rst

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@@ -0,0 +1,251 @@
1+
============================
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LLVM |release| Release Notes
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============================
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.. contents::
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:local:
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8+
.. only:: PreRelease
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.. warning::
11+
These are in-progress notes for the upcoming LLVM |version| release.
12+
Release notes for previous releases can be found on
13+
`the Download Page <https://releases.llvm.org/download.html>`_.
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15+
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Introduction
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============
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19+
This document contains the release notes for the LLVM Compiler Infrastructure,
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release |release|. Here we describe the status of LLVM, including major improvements
21+
from the previous release, improvements in various subprojects of LLVM, and
22+
some of the current users of the code. All LLVM releases may be downloaded
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from the `LLVM releases web site <https://llvm.org/releases/>`_.
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For more information about LLVM, including information about the latest
26+
release, please check out the `main LLVM web site <https://llvm.org/>`_. If you
27+
have questions or comments, the `Discourse forums
28+
<https://discourse.llvm.org>`_ is a good place to ask
29+
them.
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31+
Note that if you are reading this file from a Git checkout or the main
32+
LLVM web page, this document applies to the *next* release, not the current
33+
one. To see the release notes for a specific release, please see the `releases
34+
page <https://llvm.org/releases/>`_.
35+
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Non-comprehensive list of changes in this release
37+
=================================================
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.. NOTE
39+
For small 1-3 sentence descriptions, just add an entry at the end of
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this list. If your description won't fit comfortably in one bullet
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point (e.g. maybe you would like to give an example of the
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functionality, or simply have a lot to talk about), see the `NOTE` below
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for adding a new subsection.
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* ...
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Update on required toolchains to build LLVM
48+
-------------------------------------------
49+
50+
Changes to the LLVM IR
51+
----------------------
52+
53+
* The ``x86_mmx`` IR type has been removed. It will be translated to
54+
the standard vector type ``<1 x i64>`` in bitcode upgrade.
55+
* Renamed ``llvm.experimental.stepvector`` intrinsic to ``llvm.stepvector``.
56+
57+
* Added ``usub_cond`` and ``usub_sat`` operations to ``atomicrmw``.
58+
59+
* Added ``U<address space>`` to data layout to represent undesirable address space
60+
if a target has it.
61+
62+
Changes to LLVM infrastructure
63+
------------------------------
64+
65+
Changes to building LLVM
66+
------------------------
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68+
Changes to TableGen
69+
-------------------
70+
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Changes to Interprocedural Optimizations
72+
----------------------------------------
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74+
Changes to the AArch64 Backend
75+
------------------------------
76+
77+
* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
78+
the required alignment space with a sequence of `0x0` bytes (the requested
79+
fill value) rather than NOPs.
80+
81+
Changes to the AMDGPU Backend
82+
-----------------------------
83+
84+
* Removed ``llvm.amdgcn.flat.atomic.fadd`` and
85+
``llvm.amdgcn.global.atomic.fadd`` intrinsics. Users should use the
86+
:ref:`atomicrmw <i_atomicrmw>` instruction with `fadd` and
87+
addrspace(0) or addrspace(1) instead.
88+
89+
Changes to the ARM Backend
90+
--------------------------
91+
92+
* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
93+
the required alignment space with a sequence of `0x0` bytes (the requested
94+
fill value) rather than NOPs.
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Changes to the AVR Backend
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--------------------------
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Changes to the DirectX Backend
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------------------------------
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Changes to the Hexagon Backend
103+
------------------------------
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105+
Changes to the LoongArch Backend
106+
--------------------------------
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Changes to the MIPS Backend
109+
---------------------------
110+
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Changes to the PowerPC Backend
112+
------------------------------
113+
114+
Changes to the RISC-V Backend
115+
-----------------------------
116+
117+
* `.balign N, 0`, `.p2align N, 0`, `.align N, 0` in code sections will now fill
118+
the required alignment space with a sequence of `0x0` bytes (the requested
119+
fill value) rather than NOPs.
120+
* Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
121+
* ``-mcpu=sifive-p470`` was added.
122+
* Added Hazard3 CPU as taped out for RP2350: ``-mcpu=rp2350-hazard3`` (32-bit
123+
only).
124+
* Fixed length vector support using RVV instructions now requires VLEN>=64. This
125+
means Zve32x and Zve32f will also require Zvl64b. The prior support was
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largely untested.
127+
* The ``Zvbc32e`` and ``Zvkgs`` extensions are now supported experimentally.
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* Added ``Smctr`` and ``Ssctr`` extensions.
129+
* ``-mcpu=syntacore-scr7`` was added.
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Changes to the WebAssembly Backend
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----------------------------------
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Changes to the Windows Target
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-----------------------------
136+
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Changes to the X86 Backend
138+
--------------------------
139+
140+
* `.balign N, 0x90`, `.p2align N, 0x90`, and `.align N, 0x90` in code sections
141+
now fill the required alignment space with repeating `0x90` bytes, rather than
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using optimised NOP filling. Optimised NOP filling fills the space with NOP
143+
instructions of various widths, not just those that use the `0x90` byte
144+
encoding. To use optimised NOP filling in a code section, leave off the
145+
"fillval" argument, i.e. `.balign N`, `.p2align N` or `.align N` respectively.
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* Due to the removal of the ``x86_mmx`` IR type, functions with
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``x86_mmx`` arguments or return values will use a different,
149+
incompatible, calling convention ABI. Such functions are not
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generally seen in the wild (Clang never generates them!), so this is
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not expected to result in real-world compatibility problems.
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* Support ISA of ``AVX10.2-256`` and ``AVX10.2-512``.
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Changes to the OCaml bindings
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-----------------------------
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Changes to the Python bindings
159+
------------------------------
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Changes to the C API
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--------------------
163+
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* The following symbols are deleted due to the removal of the ``x86_mmx`` IR type:
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* ``LLVMX86_MMXTypeKind``
167+
* ``LLVMX86MMXTypeInContext``
168+
* ``LLVMX86MMXType``
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* The following functions are added to further support non-null-terminated strings:
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* ``LLVMGetNamedFunctionWithLength``
173+
* ``LLVMGetNamedGlobalWithLength``
174+
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* The following functions are added to access the ``LLVMContextRef`` associated
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with ``LLVMValueRef`` and ``LLVMBuilderRef`` objects:
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* ``LLVMGetValueContext``
179+
* ``LLVMGetBuilderContext``
180+
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* The new pass manager can now be invoked with a custom alias analysis pipeline, using
182+
the ``LLVMPassBuilderOptionsSetAAPipeline`` function.
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* It is now also possible to run the new pass manager on a single function, by calling
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``LLVMRunPassesOnFunction`` instead of ``LLVMRunPasses``.
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* Support for creating instructions with custom synchronization scopes has been added:
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* ``LLVMGetSyncScopeID`` to map a synchronization scope name to an ID.
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* ``LLVMBuildFenceSyncScope``, ``LLVMBuildAtomicRMWSyncScope`` and
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``LLVMBuildAtomicCmpXchgSyncScope`` versions of the existing builder functions
192+
with an additional synchronization scope ID parameter.
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* ``LLVMGetAtomicSyncScopeID`` and ``LLVMSetAtomicSyncScopeID`` to get and set the
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synchronization scope of any atomic instruction.
195+
* ``LLVMIsAtomic`` to check if an instruction is atomic, for use with the above functions.
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Because of backwards compatibility, ``LLVMIsAtomicSingleThread`` and
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``LLVMSetAtomicSingleThread`` continue to work with any instruction type.
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* The `LLVMSetPersonalityFn` and `LLVMSetInitializer` APIs now support clearing the
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personality function and initializer respectively by passing a null pointer.
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* The following functions are added to allow iterating over debug records attached to
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instructions:
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* ``LLVMGetFirstDbgRecord``
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* ``LLVMGetLastDbgRecord``
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* ``LLVMGetNextDbgRecord``
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* ``LLVMGetPreviousDbgRecord``
209+
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Changes to the CodeGen infrastructure
212+
-------------------------------------
213+
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Changes to the Metadata Info
215+
---------------------------------
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Changes to the Debug Info
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---------------------------------
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Changes to the LLVM tools
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---------------------------------
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Changes to LLDB
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---------------------------------
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Changes to BOLT
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---------------------------------
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Changes to Sanitizers
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---------------------
231+
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Other Changes
233+
-------------
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External Open Source Projects Using LLVM 19
236+
===========================================
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* A project...
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Additional Information
241+
======================
242+
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A wide variety of additional information is available on the `LLVM web page
244+
<https://llvm.org/>`_, in particular in the `documentation
245+
<https://llvm.org/docs/>`_ section. The web page also contains versions of the
246+
API documentation which is up-to-date with the Git version of the source
247+
code. You can access versions of these documents specific to this release by
248+
going into the ``llvm/docs/`` directory in the LLVM tree.
249+
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If you have any questions or comments about LLVM, please feel free to contact
251+
us via the `Discourse forums <https://discourse.llvm.org>`_.

llvm/include/llvm/IR/DataLayout.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -94,6 +94,7 @@ class DataLayout {
9494
unsigned AllocaAddrSpace = 0;
9595
unsigned ProgramAddrSpace = 0;
9696
unsigned DefaultGlobalsAddrSpace = 0;
97+
std::optional<unsigned> UndesirableAddressSpace;
9798

9899
MaybeAlign StackNaturalAlign;
99100
MaybeAlign FunctionPtrAlign;
@@ -245,6 +246,9 @@ class DataLayout {
245246
unsigned getDefaultGlobalsAddressSpace() const {
246247
return DefaultGlobalsAddrSpace;
247248
}
249+
std::optional<unsigned> getUndesirableAddressSpace() const {
250+
return UndesirableAddressSpace;
251+
}
248252

249253
bool hasMicrosoftFastStdCallMangling() const {
250254
return ManglingMode == MM_WinCOFFX86;

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