Perform S32 G_ADD instead of unpacked addition for V2S16

Author: gandhi56

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp

@@ -501,16 +501,10 @@ void RegBankLegalizeHelper::lowerUnpackMinMax(MachineInstr &MI) {
 }
 
 void RegBankLegalizeHelper::lowerScalarizeV2S16(MachineInstr &MI) {
-  // Unpack the V2S16 operands into two S16 scalars each
-  auto Op1 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(1).getReg());
-  auto Op2 = B.buildUnmerge({SgprRB, S16}, MI.getOperand(2).getReg());
-
-  // Perform scalar additions on S16 values
-  Register Lo = B.buildInstr(MI.getOpcode(), {SgprRB_S16}, {Op1.getReg(0), Op2.getReg(0)}).getReg(0);
-  Register Hi = B.buildInstr(MI.getOpcode(), {SgprRB_S16}, {Op1.getReg(1), Op2.getReg(1)}).getReg(0);
-  
-  // Pack the results back into V2S16
-  B.buildBuildVectorTrunc(MI.getOperand(0).getReg(), {Lo, Hi});
+  auto CastOp1 = B.buildBitcast(SgprRB_S32, MI.getOperand(1).getReg());
+  auto CastOp2 = B.buildBitcast(SgprRB_S32, MI.getOperand(2).getReg());
+  auto NewInstr = B.buildInstr(MI.getOpcode(), {SgprRB_S32}, {CastOp1, CastOp2});
+  B.buildBitcast({SgprRB, V2S16}, NewInstr.getReg(0));
   MI.eraseFromParent();
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir

@@ -14,12 +14,11 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s16), [[UV1:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:sgpr(s16), [[UV3:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s16) = G_ADD [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s16) = G_ADD [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[ADD]](s16), [[ADD1]](s16)
-    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s16>)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[ADD]](s32)
+    ; CHECK-NEXT: S_ENDPGM 0, implicit %2:sgpr(<2 x s16>)
     %0:_(<2 x s16>) = COPY $sgpr0
     %1:_(<2 x s16>) = COPY $sgpr1
     %2:_(<2 x s16>) = G_ADD %0, %1

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.v2s16.mir

@@ -14,12 +14,11 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s16), [[UV1:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:sgpr(s16), [[UV3:%[0-9]+]]:sgpr(s16) = G_UNMERGE_VALUES [[COPY1]](<2 x s16>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:sgpr(s16) = G_SUB [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:sgpr(s16) = G_SUB [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[SUB]](s16), [[SUB1]](s16)
-    ; CHECK-NEXT: S_ENDPGM 0, implicit [[BUILD_VECTOR]](<2 x s16>)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](<2 x s16>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY1]](<2 x s16>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:sgpr(s32) = G_SUB [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[SUB]](s32)
+    ; CHECK-NEXT: S_ENDPGM 0, implicit %2:sgpr(<2 x s16>)
     %0:_(<2 x s16>) = COPY $sgpr0
     %1:_(<2 x s16>) = COPY $sgpr1
     %2:_(<2 x s16>) = G_SUB %0, %1