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SpencerAbsonSpencerAbson
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simplify implementation of new patterns
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+49
-77
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2 files changed

+49
-77
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 34 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -7222,101 +7222,58 @@ def : Pat<(v2i64 (int_aarch64_neon_vcopy_lane
72227222
V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
72237223
)>;
72247224

7225-
// Insert an extracted vector element into a 128-bit Neon vector
7226-
multiclass Neon_INS_elt_pattern_v128<ValueType VT128, ValueType VT64, ValueType VTSVE,
7227-
ValueType VTScal, Operand ExIdxTy, Instruction INS> {
7228-
// Extracting from the lower 128-bits of an SVE vector
7225+
// Move elements between vectors
7226+
multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, ValueType VTSVE,
7227+
ValueType VTScal, Operand SVEIdxTy, Instruction INS> {
7228+
// Extracting from the lowest 128-bits of an SVE vector
72297229
def : Pat<(VT128 (vector_insert VT128:$Rn,
7230-
(VTScal (vector_extract VTSVE:$Rm, (i64 ExIdxTy:$Immn))),
7230+
(VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),
72317231
(i64 imm:$Immd))),
7232-
(INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), ExIdxTy:$Immn)>;
7232+
(INS VT128:$Rn, imm:$Immd, (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn)>;
72337233

7234-
// Extracting from another Neon vector
7235-
def : Pat<(VT128 (vector_insert V128:$Rn,
7236-
(VTScal (vector_extract (VT128 V128:$Rm), (i64 imm:$Immn))),
7237-
(i64 imm:$Immd))),
7238-
(INS V128:$Rn, imm:$Immd, V128:$Rm, imm:$Immn)>;
7239-
7240-
def : Pat<(VT128 (vector_insert V128:$Rn,
7241-
(VTScal (vector_extract (VT64 V64:$Rm), (i64 imm:$Immn))),
7242-
(i64 imm:$Immd))),
7243-
(INS V128:$Rn, imm:$Immd,
7244-
(SUBREG_TO_REG (i64 0), V64:$Rm, dsub), imm:$Immn)>;
7245-
}
7246-
7247-
// Insert an extracted vector element into a 64-bit Neon vector
7248-
multiclass Neon_INS_elt_pattern_v64<ValueType VT128, ValueType VT64, ValueType VTSVE,
7249-
ValueType VTScal, Operand ExIdxTy, Instruction INS> {
7250-
// Extracting from the lower 128-bits of an SVE vector
72517234
def : Pat<(VT64 (vector_insert VT64:$Rn,
7252-
(VTScal (vector_extract VTSVE:$Rm, (i64 ExIdxTy:$Immn))),
7235+
(VTScal (vector_extract VTSVE:$Rm, (i64 SVEIdxTy:$Immn))),
72537236
(i64 imm:$Immd))),
7254-
(EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), VT64:$Rn, dsub), imm:$Immd,
7255-
(VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), ExIdxTy:$Immn),
7256-
dsub)>;
7257-
7258-
// Extracting from another Neon vector
7259-
def : Pat<(VT64 (vector_insert V64:$Rn,
7260-
(VTScal (vector_extract (VT128 V128:$Rm), (i64 imm:$Immn))),
7237+
(EXTRACT_SUBREG
7238+
(INS (SUBREG_TO_REG (i64 0), VT64:$Rn, dsub), imm:$Immd,
7239+
(VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)), SVEIdxTy:$Immn),
7240+
dsub)>;
7241+
// Extracting from another NEON vector
7242+
def : Pat<(VT128 (vector_insert V128:$src,
7243+
(VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),
72617244
(i64 imm:$Immd))),
7262-
(EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$Rn, dsub),
7263-
imm:$Immd, V128:$Rm, imm:$Immn),
7264-
dsub)>;
7245+
(INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
72657246

7266-
def : Pat<(VT64 (vector_insert V64:$Rn,
7267-
(VTScal (vector_extract (VT64 V64:$Rm), (i64 imm:$Immn))),
7247+
def : Pat<(VT128 (vector_insert V128:$src,
7248+
(VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),
72687249
(i64 imm:$Immd))),
7269-
(EXTRACT_SUBREG
7270-
(INS (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immd,
7271-
(SUBREG_TO_REG (i64 0), V64:$Rm, dsub), imm:$Immn),
7272-
dsub)>;
7273-
}
7274-
7275-
// Special case for <1 x double/i64> - insertion may be vector_from_scalar or
7276-
// (vector_insert (vec) 0).
7277-
multiclass Neon_INS_elt_pattern_v64d<ValueType VT128, ValueType VT64, ValueType VTSVE,
7278-
ValueType VTScal> {
7279-
// Extracting from the lower 128-bits of an SVE vector
7280-
def : Pat<(VT64 (vec_ins_or_scal_vec
7281-
(VTScal (vector_extract VTSVE:$Rm, VectorIndexD:$Immn)))),
7282-
(EXTRACT_SUBREG
7283-
(INSvi64lane (IMPLICIT_DEF), 0, (VT128 (EXTRACT_SUBREG VTSVE:$Rm, zsub)),
7284-
VectorIndexD:$Immn),
7285-
dsub)>;
7250+
(INS V128:$src, imm:$Immd,
7251+
(SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
72867252

7287-
def : Pat<(VT64 (vec_ins_or_scal_vec
7288-
(VTScal (vector_extract (VT128 V128:$Rm), (i64 imm:$Immn))))),
7289-
(EXTRACT_SUBREG
7290-
(INSvi64lane (IMPLICIT_DEF), (i64 0), V128:$Rm, imm:$Immn),
7291-
dsub)>;
7253+
def : Pat<(VT64 (vector_insert V64:$src,
7254+
(VTScal (vector_extract (VT128 V128:$Rn), (i64 imm:$Immn))),
7255+
(i64 imm:$Immd))),
7256+
(EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
7257+
imm:$Immd, V128:$Rn, imm:$Immn),
7258+
dsub)>;
72927259

7293-
// Extracting from another NEON vector
7294-
def : Pat<(VT64 (vec_ins_or_scal_vec
7295-
(VTScal (vector_extract (VT64 V64:$Rm), (i64 imm:$Immn))))),
7260+
def : Pat<(VT64 (vector_insert V64:$src,
7261+
(VTScal (vector_extract (VT64 V64:$Rn), (i64 imm:$Immn))),
7262+
(i64 imm:$Immd))),
72967263
(EXTRACT_SUBREG
7297-
(INSvi64lane (IMPLICIT_DEF), (i64 0),
7298-
(SUBREG_TO_REG (i64 0), V64:$Rm, dsub), imm:$Immn),
7264+
(INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
7265+
(SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
72997266
dsub)>;
73007267
}
73017268

7302-
multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64, ValueType SVESrcVT,
7303-
ValueType VTScal, Operand ExIdxTy, Instruction INS> {
7304-
defm : Neon_INS_elt_pattern_v64<VT128, VT64, SVESrcVT, VTScal, ExIdxTy, INS>;
7305-
defm : Neon_INS_elt_pattern_v128<VT128, VT64, SVESrcVT, VTScal, ExIdxTy, INS>;
7306-
}
7307-
7308-
defm : Neon_INS_elt_pattern<v4f32, v2f32, nxv4f32, f32, VectorIndexS, INSvi32lane>;
7269+
defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane>;
73097270
defm : Neon_INS_elt_pattern<v8f16, v4f16, nxv8f16, f16, VectorIndexH, INSvi16lane>;
73107271
defm : Neon_INS_elt_pattern<v8bf16, v4bf16, nxv8bf16, bf16, VectorIndexH, INSvi16lane>;
7311-
defm : Neon_INS_elt_pattern<v4f32, v2f32, nxv4f32, f32, VectorIndexS, INSvi32lane>;
73127272
defm : Neon_INS_elt_pattern<v16i8, v8i8, nxv16i8, i32, VectorIndexB, INSvi8lane>;
7313-
defm : Neon_INS_elt_pattern<v8i16, v4i16, nxv8i16, i32, VectorIndexH, INSvi16lane>;
7273+
defm : Neon_INS_elt_pattern<v4f32, v2f32, nxv4f32, f32, VectorIndexS, INSvi32lane>;
73147274
defm : Neon_INS_elt_pattern<v4i32, v2i32, nxv4i32, i32, VectorIndexS, INSvi32lane>;
7315-
7316-
defm : Neon_INS_elt_pattern_v128<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi64lane>;
7317-
defm : Neon_INS_elt_pattern_v64d<v2f64, v1f64, nxv2f64, f64>;
7318-
defm : Neon_INS_elt_pattern_v128<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane>;
7319-
defm : Neon_INS_elt_pattern_v64d<v2i64, v1i64, nxv2i64, i64>;
7275+
defm : Neon_INS_elt_pattern<v2f64, v1f64, nxv2f64, f64, VectorIndexD, INSvi64lane>;
7276+
defm : Neon_INS_elt_pattern<v2i64, v1i64, nxv2i64, i64, VectorIndexD, INSvi64lane>;
73207277

73217278
// Insert from bitcast
73227279
// vector_insert(bitcast(f32 src), n, lane) -> INSvi32lane(src, lane, INSERT_SUBREG(-, n), 0)

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3365,6 +3365,21 @@ let Predicates = [HasSVEorSME] in {
33653365
(UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>;
33663366
def : Pat<(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)),
33673367
(UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>;
3368+
3369+
// Move element from the bottom 128-bits of a scalable vector to a single-element vector.
3370+
// Alternative case where insertelement is just scalar_to_vector rather than vector_insert.
3371+
def : Pat<(v1f64 (scalar_to_vector
3372+
(f64 (vector_extract nxv2f64:$vec, VectorIndexD:$index)))),
3373+
(EXTRACT_SUBREG
3374+
(INSvi64lane (IMPLICIT_DEF), (i64 0),
3375+
(EXTRACT_SUBREG nxv2f64:$vec, zsub), VectorIndexD:$index),
3376+
dsub)>;
3377+
def : Pat<(v1i64 (scalar_to_vector
3378+
(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)))),
3379+
(EXTRACT_SUBREG
3380+
(INSvi64lane (IMPLICIT_DEF), (i64 0),
3381+
(EXTRACT_SUBREG nxv2i64:$vec, zsub), VectorIndexD:$index),
3382+
dsub)>;
33683383
} // End HasNEON
33693384

33703385
let Predicates = [HasNEON] in {

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