[RISCV] Add tune info for postra scheduling direction

The results differ on different platforms so it is really hard to
determine a common default value.

Tune info for postra scheduling direction is added and CPUs can
set their own preferable postra scheduling direction.

We set the default value to `bidirectional` as it may be the most
balanced direction.

Author: wangpc-pp

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -123,6 +123,14 @@ class TargetInstrInfo;
 class TargetPassConfig;
 class TargetRegisterInfo;
 
+namespace MISchedPostRASched {
+enum Direction {
+  TopDown,
+  BottomUp,
+  Bidirectional,
+};
+} // end namespace MISchedPostRASched
+
 /// MachineSchedContext provides enough context from the MachineScheduler pass
 /// for the target to instantiate a scheduler.
 struct MachineSchedContext {

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -81,13 +81,7 @@ cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
                            cl::desc("Force top-down list scheduling"));
 cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
                             cl::desc("Force bottom-up list scheduling"));
-namespace MISchedPostRASched {
-enum Direction {
-  TopDown,
-  BottomUp,
-  Bidirectional,
-};
-} // end namespace MISchedPostRASched
+
 cl::opt<MISchedPostRASched::Direction> PostRADirection(
     "misched-postra-direction", cl::Hidden,
     cl::desc("Post reg-alloc list scheduling direction"),

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -10,6 +10,11 @@
 // RISC-V processors supported.
 //===----------------------------------------------------------------------===//
 
+// Predefined scheduling direction.
+defvar TopDown       = [{ MISchedPostRASched::TopDown }];
+defvar BottomUp      = [{ MISchedPostRASched::BottomUp }];
+defvar Bidirectional = [{ MISchedPostRASched::Bidirectional }];
+
 class RISCVTuneInfo {
   bits<8> PrefFunctionAlignment = 1;
   bits<8> PrefLoopAlignment = 1;
@@ -37,6 +42,11 @@ class RISCVTuneInfo {
 
   bits<32> MaxLoadsPerMemcmpOptSize = 4;
   bits<32> MaxLoadsPerMemcmp = 8;
+
+  // The direction of PostRA scheduling.
+  // Do bidirectional scheduling by default since it provides a more balanced
+  // scheduling leading to better performance. This will increase compile time.
+  code PostRASchedDirection = Bidirectional;
 }
 
 def RISCVTuneInfoTable : GenericTable {
@@ -49,7 +59,8 @@ def RISCVTuneInfoTable : GenericTable {
                 "MaxStoresPerMemset", "MaxGluedStoresPerMemcpy",
                 "MaxStoresPerMemcpyOptSize", "MaxStoresPerMemcpy",
                 "MaxStoresPerMemmoveOptSize", "MaxStoresPerMemmove",
-                "MaxLoadsPerMemcmpOptSize", "MaxLoadsPerMemcmp"];
+                "MaxLoadsPerMemcmpOptSize", "MaxLoadsPerMemcmp",
+                "PostRASchedDirection"];
 }
 
 def getRISCVTuneInfo : SearchIndex {

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

@@ -16,7 +16,6 @@
 #include "RISCV.h"
 #include "RISCVFrameLowering.h"
 #include "RISCVTargetMachine.h"
-#include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/MacroFusion.h"
 #include "llvm/CodeGen/ScheduleDAGMutation.h"
 #include "llvm/MC/TargetRegistry.h"
@@ -211,3 +210,19 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
   // register-pressure tracking. This will increase compile time.
   Policy.ShouldTrackPressure = true;
 }
+
+void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                               unsigned NumRegionInstrs) const {
+  MISchedPostRASched::Direction PostRASchedDirection =
+      getPostRASchedDirection();
+  if (PostRASchedDirection == MISchedPostRASched::TopDown) {
+    Policy.OnlyTopDown = true;
+    Policy.OnlyBottomUp = false;
+  } else if (PostRASchedDirection == MISchedPostRASched::BottomUp) {
+    Policy.OnlyTopDown = false;
+    Policy.OnlyBottomUp = true;
+  } else if (PostRASchedDirection == MISchedPostRASched::Bidirectional) {
+    Policy.OnlyTopDown = false;
+    Policy.OnlyBottomUp = false;
+  }
+}

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -21,6 +21,7 @@
 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
+#include "llvm/CodeGen/MachineScheduler.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
@@ -66,6 +67,9 @@ struct RISCVTuneInfo {
 
   unsigned MaxLoadsPerMemcmpOptSize;
   unsigned MaxLoadsPerMemcmp;
+
+  // The direction of PostRA scheduling.
+  MISchedPostRASched::Direction PostRASchedDirection;
 };
 
 #define GET_RISCVTuneInfoTable_DECL
@@ -362,8 +366,15 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
                    : TuneInfo->MaxLoadsPerMemcmp;
   }
 
+  MISchedPostRASched::Direction getPostRASchedDirection() const {
+    return TuneInfo->PostRASchedDirection;
+  }
+
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
                            unsigned NumRegionInstrs) const override;
+
+  void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                 unsigned NumRegionInstrs) const override;
 };
 } // End llvm namespace
 

llvm/test/CodeGen/RISCV/machine-combiner-strategies.ll

@@ -50,8 +50,8 @@ define i32 @test_local_strategy(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32
 ; CHECK_LOCAL_SIFIVE_U74-NEXT:  # %bb.1: # %b2
 ; CHECK_LOCAL_SIFIVE_U74-NEXT:    ret
 ; CHECK_LOCAL_SIFIVE_U74-NEXT:  .LBB0_2: # %b1
-; CHECK_LOCAL_SIFIVE_U74-NEXT:    add a3, a3, a4
 ; CHECK_LOCAL_SIFIVE_U74-NEXT:    add a0, a0, a5
+; CHECK_LOCAL_SIFIVE_U74-NEXT:    add a3, a3, a4
 ; CHECK_LOCAL_SIFIVE_U74-NEXT:    addw a0, a0, a3
 ; CHECK_LOCAL_SIFIVE_U74-NEXT:    ret
 ;