|
| 1 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64 |
| 2 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+no-zcz-fpr64,+fullfp16 | FileCheck %s -check-prefixes=ALL,NOZCZ-FPR64-FULLFP16 |
| 3 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64 |
| 4 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+fullfp16 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64 |
| 5 | +; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,FP-WORKAROUND |
| 6 | +; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64 |
| 7 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64 |
| 8 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64 |
| 9 | +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-FPR64 |
| 10 | + |
| 11 | +define half @tf16() { |
| 12 | +entry: |
| 13 | +; ALL-LABEL: tf16: |
| 14 | +; FP-WORKAROUND: mov s0, wzr |
| 15 | +; NOZCZ-FPR64: mov s0, wzr |
| 16 | +; NOZCZ-FPR64-FULLFP16: mov h0, wzr |
| 17 | +; ZCZ-FPR64: movi d0, #0 |
| 18 | + ret half 0.0 |
| 19 | +} |
| 20 | + |
| 21 | +define float @tf32() { |
| 22 | +entry: |
| 23 | +; ALL-LABEL: tf32: |
| 24 | +; FP-WORKAROUND: mov s0, wzr |
| 25 | +; NOZCZ-FPR64: mov s0, wzr |
| 26 | +; ZCZ-FPR64: movi d0, #0 |
| 27 | + ret float 0.0 |
| 28 | +} |
| 29 | + |
| 30 | +define double @td64() { |
| 31 | +entry: |
| 32 | +; ALL-LABEL: td64: |
| 33 | +; FP-WORKAROUND: mov d0, xzr |
| 34 | +; NOZCZ-FPR64: mov d0, xzr |
| 35 | +; ZCZ-FPR64: movi d0, #0 |
| 36 | + ret double 0.0 |
| 37 | +} |
| 38 | + |
| 39 | +define <8 x i8> @tv8i8() { |
| 40 | +entry: |
| 41 | +; ALL-LABEL: tv8i8: |
| 42 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 43 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 44 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 45 | + ret <8 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> |
| 46 | +} |
| 47 | + |
| 48 | +define <4 x i16> @tv4i16() { |
| 49 | +entry: |
| 50 | +; ALL-LABEL: tv4i16: |
| 51 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 52 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 53 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 54 | + ret <4 x i16> <i16 0, i16 0, i16 0, i16 0> |
| 55 | +} |
| 56 | + |
| 57 | +define <2 x i32> @tv2i32() { |
| 58 | +entry: |
| 59 | +; ALL-LABEL: tv2i32: |
| 60 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 61 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 62 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 63 | + ret <2 x i32> <i32 0, i32 0> |
| 64 | +} |
| 65 | + |
| 66 | +define <2 x float> @tv2f32() { |
| 67 | +entry: |
| 68 | +; ALL-LABEL: tv2f32: |
| 69 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 70 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 71 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 72 | + ret <2 x float> <float 0.0, float 0.0> |
| 73 | +} |
| 74 | + |
| 75 | +define <16 x i8> @tv16i8() { |
| 76 | +entry: |
| 77 | +; ALL-LABEL: tv16i8: |
| 78 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 79 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 80 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 81 | + ret <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0> |
| 82 | +} |
| 83 | + |
| 84 | +define <8 x i16> @tv8i16() { |
| 85 | +entry: |
| 86 | +; ALL-LABEL: tv8i16: |
| 87 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 88 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 89 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 90 | + ret <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> |
| 91 | +} |
| 92 | + |
| 93 | +define <4 x i32> @tv4i32() { |
| 94 | +entry: |
| 95 | +; ALL-LABEL: tv4i32: |
| 96 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 97 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 98 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 99 | + ret <4 x i32> <i32 0, i32 0, i32 0, i32 0> |
| 100 | +} |
| 101 | + |
| 102 | +define <2 x i64> @tv2i64() { |
| 103 | +entry: |
| 104 | +; ALL-LABEL: tv2i64: |
| 105 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 106 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 107 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 108 | + ret <2 x i64> <i64 0, i64 0> |
| 109 | +} |
| 110 | + |
| 111 | +define <4 x float> @tv4f32() { |
| 112 | +entry: |
| 113 | +; ALL-LABEL: tv4f32: |
| 114 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 115 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 116 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 117 | + ret <4 x float> <float 0.0, float 0.0, float 0.0, float 0.0> |
| 118 | +} |
| 119 | + |
| 120 | +define <2 x double> @tv2d64() { |
| 121 | +entry: |
| 122 | +; ALL-LABEL: tv2d64: |
| 123 | +; FP-WORKAROUND: movi{{(.16b)?}} v0{{(.16b)?}}, #0 |
| 124 | +; NOZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 125 | +; ZCZ-FPR64: movi{{(.2d)?}} v0{{(.2d)?}}, #0 |
| 126 | + ret <2 x double> <double 0.0, double 0.0> |
| 127 | +} |
| 128 | + |
| 129 | +; We used to produce spills+reloads for a Q register with zero cycle zeroing |
| 130 | +; enabled. |
| 131 | +; ALL-LABEL: foo: |
| 132 | +; ALL-NOT: str q{{[0-9]+}} |
| 133 | +; ALL-NOT: ldr q{{[0-9]+}} |
| 134 | +define double @foo(i32 %n) { |
| 135 | +entry: |
| 136 | + br label %for.body |
| 137 | + |
| 138 | +for.body: |
| 139 | + %phi0 = phi double [ 1.0, %entry ], [ %v0, %for.body ] |
| 140 | + %i.076 = phi i32 [ 0, %entry ], [ %inc, %for.body ] |
| 141 | + %conv21 = sitofp i32 %i.076 to double |
| 142 | + %call = tail call fast double @sin(double %conv21) |
| 143 | + %cmp.i = fcmp fast olt double %phi0, %call |
| 144 | + %v0 = select i1 %cmp.i, double %call, double %phi0 |
| 145 | + %inc = add nuw nsw i32 %i.076, 1 |
| 146 | + %cmp = icmp slt i32 %inc, %n |
| 147 | + br i1 %cmp, label %for.body, label %for.end |
| 148 | + |
| 149 | +for.end: |
| 150 | + ret double %v0 |
| 151 | +} |
| 152 | + |
| 153 | +declare double @sin(double) |
0 commit comments