Use S-expressions instead

Author: linuxrocks123

llvm/lib/Target/AMDGPU/SOPInstructions.td

@@ -265,11 +265,9 @@ def S_BREV_B64 : SOP1_64 <"s_brev_b64",
 
 let Defs = [SCC] in {
 def S_BCNT0_I32_B32 : SOP1_32 <"s_bcnt0_i32_b32",
-  [(set i32:$sdst, (UniformUnaryFrag<int_amdgcn_bcnt32_lo> i32:$src0))]
->;
-def S_BCNT0_I32_B64 : SOP1_32_64 <"s_bcnt0_i32_b64",
-  [(set i32:$sdst, (UniformUnaryFrag<int_amdgcn_bcnt64_lo> i64:$src0))]
+  [(set i32:$sdst, (UniformBinFrag<sub> 32, (UniformUnaryFrag<ctpop> i32:$src0)))]
 >;
+def S_BCNT0_I32_B64 : SOP1_32_64 <"s_bcnt0_i32_b64">;
 def S_BCNT1_I32_B32 : SOP1_32 <"s_bcnt1_i32_b32",
   [(set i32:$sdst, (UniformUnaryFrag<ctpop> i32:$src0))]
 >;
@@ -1888,6 +1886,13 @@ def : GCNPat <
      (S_MOV_B32 (i32 0)), sub1))
 >;
 
+def : GCNPat <
+   (i64 (UniformBinFrag<sub> 64, (UniformUnaryFrag<ctpop> i64:$src))),
+    (i64 (REG_SEQUENCE SReg_64,
+     (i32 (COPY_TO_REGCLASS (S_BCNT0_I32_B64 $src), SReg_32)), sub0,
+     (S_MOV_B32 (i32 0)), sub1))
+>;
+
 def : GCNPat <
   (i32 (UniformBinFrag<smax> i32:$x, (i32 (ineg i32:$x)))),
   (S_ABS_I32 SReg_32:$x)

llvm/test/CodeGen/AMDGPU/s_cmp_0.ll

@@ -465,6 +465,7 @@ define amdgpu_ps i32 @bcnt064(i64 inreg %val0) {
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT: s_bcnt0_i32_b64 s0, s[0:1]
 ; CHECK-NEXT: s_mov_b32 s1, 0
+; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
 ; CHECK-NEXT: ;;#ASMSTART
 ; CHECK-NEXT: ; use s[0:1]
 ; CHECK-NEXT: ;;#ASMEND
@@ -682,19 +683,18 @@ define amdgpu_ps void @bcnt064_not_for_vregs(ptr addrspace(1) %out, ptr addrspac
 define amdgpu_ps i32 @bcnt032_ctpop_multiple_uses(i32 inreg %val0) {
 ; CHECK-LABEL: bcnt032_ctpop_multiple_uses:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT: _i32_b32 s0, s0
-; CHECK-NEXT: 32 s1, 32, s0
-; CHECK-NEXT: g_u32 s1, 0
-; CHECK-NEXT: TART
-; CHECK-NEXT: 0
-; CHECK-NEXT: ND
-; CHECK-NEXT: TART
-; CHECK-NEXT: 1
-; CHECK-NEXT: ND
-; CHECK-NEXT: ct_b64 s[0:1], -1, 0
-; CHECK-NEXT: sk_b32_e64 v0, 0, 1, s[0:1]
-; CHECK-NEXT: irstlane_b32 s0, v0
-; CHECK-NEXT: n to shader part epilog
+; CHECK-NEXT: s_bcnt1_i32_b32 s1, s0
+; CHECK-NEXT: s_bcnt0_i32_b32 s0, s0
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s1
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s0
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: ; return to shader part epilog
   %result = call i32 @llvm.ctpop.i32(i32 %val0) nounwind readnone
   %result2 = sub i32 32, %result
   call void asm "; use $0", "s"(i32 %result)
@@ -707,21 +707,21 @@ define amdgpu_ps i32 @bcnt032_ctpop_multiple_uses(i32 inreg %val0) {
 define amdgpu_ps i32 @bcnt064_ctpop_multiple_uses(i64 inreg %val0) {
 ; CHECK-LABEL: bcnt064_ctpop_multiple_uses:
 ; CHECK:       ; %bb.0:
-; CHECK-NEXT: _i32_b64 s0, s[0:1]
-; CHECK-NEXT: 32 s2, 64, s0
-; CHECK-NEXT: u32 s3, 0, 0
-; CHECK-NEXT: 32 s1, 0
-; CHECK-NEXT: g_u64 s[2:3], 0
-; CHECK-NEXT: TART
-; CHECK-NEXT: [0:1]
-; CHECK-NEXT: ND
-; CHECK-NEXT: ct_b64 s[0:1], -1, 0
-; CHECK-NEXT: sk_b32_e64 v0, 0, 1, s[0:1]
-; CHECK-NEXT: irstlane_b32 s0, v0
-; CHECK-NEXT: TART
-; CHECK-NEXT: [2:3]
-; CHECK-NEXT: ND
-; CHECK-NEXT: n to shader part epilog
+; CHECK-NEXT: s_mov_b32 s3, 0
+; CHECK-NEXT: s_bcnt1_i32_b64 s2, s[0:1]
+; CHECK-NEXT: s_bcnt0_i32_b64 s0, s[0:1]
+; CHECK-NEXT: s_mov_b32 s1, s3
+; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s[0:1]
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; CHECK-NEXT: v_readfirstlane_b32 s0, v0
+; CHECK-NEXT: ;;#ASMSTART
+; CHECK-NEXT: ; use s[2:3]
+; CHECK-NEXT: ;;#ASMEND
+; CHECK-NEXT: ; return to shader part epilog
   %result = call i64 @llvm.ctpop.i64(i64 %val0) nounwind readnone
   %result2 = sub i64 64, %result
   call void asm "; use $0", "s"(i64 %result)