remove a chance to restructure a block ending with OpBranchConditional

Author: VyacheslavLevytskyy

llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp

@@ -191,19 +191,19 @@ bool SPIRVInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
   auto MI = MBB.getLastNonDebugInstr();
   if (!MI.isValid())
     return false;
-  if (MI->getOpcode() == SPIRV::OpBranch) {
-    TBB = MI->getOperand(0).getMBB();
-    return false;
-  } else if (MI->getOpcode() == SPIRV::OpBranchConditional) {
-    Cond.push_back(MI->getOperand(0));
-    TBB = MI->getOperand(1).getMBB();
-    FBB = MI->getOperand(2).getMBB();
-    for (unsigned I = 3, E = MI->getNumOperands(); I < E; ++I)
-      Cond.push_back(MI->getOperand(I));
-    return false;
-  } else {
+
+  // We do not allow to restructure blocks ending with OpBranchConditional,
+  // because there is no way to encode `if (Cond) then Stmt` logic, only
+  // full if-then-else is supported by OpBranchConditional.
+  // If we supported splitting of blocks ending with OpBranchConditional
+  // MachineBasicBlock.cpp would expect successfull implementation of calls
+  // to insertBranch() setting FBB to null that is not feasible.
+  if (MI->getOpcode() != SPIRV::OpBranch)
     return true;
-  }
+
+  // Allow only 'unconditional branch' modifications of the basic block.
+  TBB = MI->getOperand(0).getMBB();
+  return false;
 }
 
 // Remove the branching code at the end of the specific MBB.
@@ -217,8 +217,7 @@ unsigned SPIRVInstrInfo::removeBranch(MachineBasicBlock &MBB,
   if (I == MBB.end())
     return 0;
 
-  unsigned Opcode = I->getOpcode();
-  if (Opcode == SPIRV::OpBranch || Opcode == SPIRV::OpBranchConditional) {
+  if (I->getOpcode() == SPIRV::OpBranch) {
     I->eraseFromParent();
     return 1;
   }
@@ -246,16 +245,7 @@ unsigned SPIRVInstrInfo::insertBranch(MachineBasicBlock &MBB,
                                       int * /*BytesAdded*/) const {
   if (!TBB)
     return 0;
-  if (Cond.empty()) {
-    BuildMI(&MBB, DL, get(SPIRV::OpBranch)).addMBB(TBB);
-  } else {
-    auto MIB = BuildMI(&MBB, DL, get(SPIRV::OpBranchConditional))
-                   .add(Cond[0])
-                   .addMBB(TBB)
-                   .addMBB(FBB);
-    for (unsigned i = 1; i < Cond.size(); ++i)
-      MIB.add(Cond[i]);
-  }
+  BuildMI(&MBB, DL, get(SPIRV::OpBranch)).addMBB(TBB);
   return 1;
 }
 

llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

@@ -622,13 +622,13 @@ def OpLoopMerge: Op<246, (outs), (ins unknown:$merge, unknown:$continue, LoopCon
 def OpSelectionMerge: Op<247, (outs), (ins unknown:$merge, SelectionControl:$sc),
                   "OpSelectionMerge $merge $sc">;
 def OpLabel: Op<248, (outs ID:$label), (ins), "$label = OpLabel">;
-let isBarrier = 1, isTerminator=1 in {
+let isBarrier = 1, isTerminator = 1, isBranch = 1 in {
   def OpBranch: Op<249, (outs), (ins unknown:$label), "OpBranch $label">;
   def OpBranchConditional: Op<250, (outs), (ins ID:$cond, unknown:$true, unknown:$false, variable_ops),
                   "OpBranchConditional $cond $true $false">;
   def OpSwitch: Op<251, (outs), (ins ID:$sel, ID:$dflt, variable_ops), "OpSwitch $sel $dflt">;
 }
-let isReturn = 1, hasDelaySlot=0, isBarrier = 0, isTerminator=1, isNotDuplicable = 1 in {
+let isReturn = 1, hasDelaySlot = 0, isBarrier = 0, isTerminator = 1, isNotDuplicable = 1 in {
   def OpKill: SimpleOp<"OpKill", 252>;
   def OpReturn: SimpleOp<"OpReturn", 253>;
   def OpReturnValue: Op<254, (outs), (ins ID:$ret), "OpReturnValue $ret">;