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AMDGPU: Select V_PK_ADD_{MIN|MAX}_{I|U}16 and V_{MIN|MAX}3_{I|U}16 on gfx1250
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‎llvm/lib/Target/AMDGPU/VOP3PInstructions.td‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -372,6 +372,30 @@ defm V_PK_MIN3_U16 : VOP3PInst<"v_pk_min3_u16", PK_ADD_MINMAX_Profile>;
372372
}
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} // End isCommutable = 1, isReMaterializable = 1
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// TODO: Extend pattern to select op_sel and op_sel_hi.
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class ThreeOp_OpSelClampPats <SDPatternOperator op1, SDPatternOperator op2,
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VOP3P_Pseudo inst,
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ValueType vt = inst.Pfl.Src0VT,
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RegisterOperand RC = getVCSrcForVT<vt>.ret> : GCNPat <
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(ThreeOpFrag<op1, op2> vt:$src0, vt:$src1, vt:$src2),
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(inst SRCMODS.OP_SEL_1, RC:$src0, SRCMODS.OP_SEL_1, RC:$src1,
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SRCMODS.OP_SEL_1, RC:$src2, DSTCLAMP.NONE, 0)
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>;
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let SubtargetPredicate = HasPkAddMinMaxInsts in {
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def : ThreeOp_OpSelClampPats<add, smax, V_PK_ADD_MAX_I16>;
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def : ThreeOp_OpSelClampPats<add, umax, V_PK_ADD_MAX_U16>;
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def : ThreeOp_OpSelClampPats<add, smin, V_PK_ADD_MIN_I16>;
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def : ThreeOp_OpSelClampPats<add, umin, V_PK_ADD_MIN_U16>;
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}
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let SubtargetPredicate = HasPkMinMax3Insts in {
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def : ThreeOp_OpSelClampPats<smax, smax, V_PK_MAX3_I16>;
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def : ThreeOp_OpSelClampPats<umax, umax, V_PK_MAX3_U16>;
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def : ThreeOp_OpSelClampPats<smin, smin, V_PK_MIN3_I16>;
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def : ThreeOp_OpSelClampPats<umin, umin, V_PK_MIN3_U16>;
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}
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// Defines patterns that extract signed 4bit from each Idx[0].
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foreach Idx = [[0,28],[4,24],[8,20],[12,16],[16,12],[20,8],[24,4]] in
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def ExtractSigned4bit_#Idx[0] : PatFrag<(ops node:$src),

‎llvm/test/CodeGen/AMDGPU/add-max.ll‎

Lines changed: 295 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,295 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GISEL %s
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define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) {
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; GCN-LABEL: add_max_u32_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, v0, v1
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_max_u32_e32 v0, v0, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umax.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) {
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; GCN-LABEL: add_max_u32_svv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, s0, v0
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_max_u32_e32 v0, v0, v1
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umax.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_u32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {
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; GCN-LABEL: add_max_u32_ssv:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_co_i32 s0, s0, s1
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; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GCN-NEXT: v_max_u32_e32 v0, s0, v0
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umax.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
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; GCN-LABEL: add_max_u32_sss:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_add_co_i32 s0, s0, s1
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; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GCN-NEXT: s_max_u32 s0, s0, s2
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; GCN-NEXT: v_mov_b32_e32 v0, s0
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umax.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) {
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; GCN-LABEL: add_max_u32_vsi:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, s0, v0
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_max_u32_e32 v0, 4, v0
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umax.i32(i32 %add, i32 4)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) {
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; GCN-LABEL: add_max_u32_svl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, s0, v0
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_max_u32_e32 v0, 0x64, v0
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umax.i32(i32 %add, i32 100)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b) {
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; GCN-LABEL: add_max_u32_slv:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_addk_co_i32 s0, 0x64
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; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GCN-NEXT: v_max_u32_e32 v0, s0, v0
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, 100
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%max = call i32 @llvm.umax.i32(i32 %add, i32 %b)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) {
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; GCN-LABEL: add_max_i32_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, v0, v1
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_max_i32_e32 v0, v0, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.smax.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) {
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; GCN-LABEL: add_min_u32_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, v0, v1
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_min_u32_e32 v0, v0, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.umin.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_min_i32_vvv(i32 %a, i32 %b, i32 %c) {
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; GCN-LABEL: add_min_i32_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_add_nc_u32_e32 v0, v0, v1
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GCN-NEXT: v_min_i32_e32 v0, v0, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add i32 %a, %b
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%max = call i32 @llvm.smin.i32(i32 %add, i32 %c)
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%ret = bitcast i32 %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
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; GCN-LABEL: add_max_v2u16_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_max_u16 v0, v0, v1, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_v2u16_svv(<2 x i16> inreg %a, <2 x i16> %b, <2 x i16> %c) {
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; GCN-LABEL: add_max_v2u16_svv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, v1
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_v2u16_ssv(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> %c) {
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; SDAG-LABEL: add_max_v2u16_ssv:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: v_pk_add_max_u16 v0, s0, s1, v0
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; SDAG-NEXT: ; return to shader part epilog
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;
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; GISEL-LABEL: add_max_v2u16_ssv:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_lshr_b32 s2, s0, 16
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; GISEL-NEXT: s_lshr_b32 s3, s1, 16
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; GISEL-NEXT: s_add_co_i32 s0, s0, s1
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; GISEL-NEXT: s_add_co_i32 s2, s2, s3
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s2
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; GISEL-NEXT: v_pk_max_u16 v0, s0, v0
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; GISEL-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_v2u16_sss(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> inreg %c) {
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; SDAG-LABEL: add_max_v2u16_sss:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: v_pk_add_u16 v0, s0, s1
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; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; SDAG-NEXT: v_pk_max_u16 v0, v0, s2
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; SDAG-NEXT: ; return to shader part epilog
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;
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; GISEL-LABEL: add_max_v2u16_sss:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_lshr_b32 s3, s0, 16
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; GISEL-NEXT: s_lshr_b32 s4, s1, 16
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; GISEL-NEXT: s_add_co_i32 s0, s0, s1
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; GISEL-NEXT: s_add_co_i32 s3, s3, s4
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s3
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; GISEL-NEXT: s_and_b32 s3, s2, 0xffff
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; GISEL-NEXT: s_lshr_b32 s1, s0, 16
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; GISEL-NEXT: s_and_b32 s0, s0, 0xffff
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; GISEL-NEXT: s_lshr_b32 s2, s2, 16
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; GISEL-NEXT: s_max_u32 s0, s0, s3
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; GISEL-NEXT: s_max_u32 s1, s1, s2
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
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; GISEL-NEXT: v_mov_b32_e32 v0, s0
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; GISEL-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
210+
}
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define amdgpu_ps float @add_max_v2u16_vsi(<2 x i16> %a, <2 x i16> inreg %b) {
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; GCN-LABEL: add_max_v2u16_vsi:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_max_u16 v0, v0, s0, 4
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> <i16 4, i16 0>)
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%ret = bitcast <2 x i16> %max to float
220+
ret float %ret
221+
}
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define amdgpu_ps float @add_max_v2u16_svl(<2 x i16> inreg %a, <2 x i16> %b) {
224+
; GCN-LABEL: add_max_v2u16_svl:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, 0x650064
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> <i16 100, i16 101>)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_v2u16_slv(<2 x i16> inreg %a, <2 x i16> %b) {
235+
; SDAG-LABEL: add_max_v2u16_slv:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: v_pk_add_max_u16 v0, 0x640064, s0, v0
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; SDAG-NEXT: ; return to shader part epilog
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;
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; GISEL-LABEL: add_max_v2u16_slv:
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; GISEL: ; %bb.0:
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; GISEL-NEXT: s_lshr_b32 s1, s0, 16
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; GISEL-NEXT: s_add_co_i32 s0, s0, 0x640064
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; GISEL-NEXT: s_addk_co_i32 s1, 0x64
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; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
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; GISEL-NEXT: v_pk_max_u16 v0, s0, v0
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; GISEL-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, <i16 100, i16 100>
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%max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %b)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_max_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
256+
; GCN-LABEL: add_max_v2s16_vvv:
257+
; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_max_i16 v0, v0, v1, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.smax.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_min_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
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; GCN-LABEL: add_min_v2u16_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_min_u16 v0, v0, v1, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.umin.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
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ret float %ret
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}
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define amdgpu_ps float @add_min_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {
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; GCN-LABEL: add_min_v2s16_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_pk_add_min_i16 v0, v0, v1, v2
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; GCN-NEXT: ; return to shader part epilog
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%add = add <2 x i16> %a, %b
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%max = call <2 x i16> @llvm.smin.v216(<2 x i16> %add, <2 x i16> %c)
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%ret = bitcast <2 x i16> %max to float
285+
ret float %ret
286+
}
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declare <2 x i16> @llvm.smin.v216(<2 x i16>, <2 x i16>)
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declare <2 x i16> @llvm.smax.v216(<2 x i16>, <2 x i16>)
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declare <2 x i16> @llvm.umin.v216(<2 x i16>, <2 x i16>)
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declare <2 x i16> @llvm.umax.v216(<2 x i16>, <2 x i16>)
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declare i32 @llvm.smin.i32(i32, i32)
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declare i32 @llvm.smax.i32(i32, i32)
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declare i32 @llvm.umin.i32(i32, i32)
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declare i32 @llvm.umax.i32(i32, i32)

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