@@ -52,12 +52,11 @@ static cl::opt<bool> PrintSlotIndexes(
5252 cl::init(true ), cl::Hidden);
5353
5454MachineBasicBlock::MachineBasicBlock (MachineFunction &MF, const BasicBlock *B)
55- : BB(B), Number(-1 ), xParent(&MF),
56- TRI(MF.getSubtarget().getRegisterInfo()) {
55+ : BB(B), Number(-1 ), xParent(&MF) {
5756 Insts.Parent = this ;
5857 if (B)
5958 IrrLoopHeaderWeight = B->getIrrLoopHeaderWeight ();
60- LiveInRegUnits.resize (TRI ->getNumRegUnits ());
59+ LiveInRegUnits.resize (MF. getSubtarget (). getRegisterInfo () ->getNumRegUnits ());
6160}
6261
6362MachineBasicBlock::~MachineBasicBlock () = default ;
@@ -601,6 +600,7 @@ void MachineBasicBlock::printAsOperand(raw_ostream &OS,
601600}
602601
603602void MachineBasicBlock::addLiveInRegUnit (MCRegister Reg, LaneBitmask LaneMask) {
603+ const TargetRegisterInfo *TRI = getParent ()->getSubtarget ().getRegisterInfo ();
604604 for (MCRegUnitMaskIterator Unit (Reg, TRI); Unit.isValid (); ++Unit) {
605605 LaneBitmask UnitMask = (*Unit).second ;
606606 if ((UnitMask & LaneMask).any ())
@@ -630,11 +630,13 @@ MachineBasicBlock::removeLiveIn(MachineBasicBlock::livein_iterator I) {
630630}
631631
632632void MachineBasicBlock::removeLiveInRegUnit (MCRegister Reg) {
633+ const TargetRegisterInfo *TRI = getParent ()->getSubtarget ().getRegisterInfo ();
633634 for (MCRegUnit Unit : TRI->regunits (Reg))
634635 LiveInRegUnits.reset (Unit);
635636}
636637
637638bool MachineBasicBlock::isLiveIn (MCRegister Reg, LaneBitmask LaneMask) const {
639+ const TargetRegisterInfo *TRI = getParent ()->getSubtarget ().getRegisterInfo ();
638640 for (MCRegUnitMaskIterator Unit (Reg, TRI); Unit.isValid (); ++Unit) {
639641 LaneBitmask UnitMask = (*Unit).second ;
640642 if ((UnitMask & LaneMask).any () && LiveInRegUnits.test ((*Unit).first ))
0 commit comments