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[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and write CSRs. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support.
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‎clang/test/Driver/print-supported-extensions-riscv.c‎

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// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
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// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
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// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
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// CHECK-NEXT: xqcicsr 0.2 'Xqcicsr' (Qualcomm uC CSR Extension)
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// CHECK-EMPTY:
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// CHECK-NEXT: Supported Profiles
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// CHECK-NEXT: rva20s64

‎llvm/docs/RISCVUsage.rst‎

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@@ -426,6 +426,9 @@ The current vendor extensions supported are:
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``Xwchc``
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LLVM implements `the custom compressed opcodes present in some QingKe cores` by WCH / Nanjing Qinheng Microelectronics. The vendor refers to these opcodes by the name "XW".
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``experimental-Xqcicsr``
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LLVM implements `version 0.2 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/latest>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. These instructions are only available for riscv32.
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Experimental C Intrinsics
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=========================
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‎llvm/docs/ReleaseNotes.md‎

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@@ -211,7 +211,8 @@ Changes to the RISC-V Backend
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* `f` and `cf` inline assembly constraints, when using F-/D-/H-in-X extensions,
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will use the relevant GPR rather than FPR. This makes inline assembly portable
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between e.g. F and Zfinx code.
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* Adds experimental assembler support for the Qualcomm uC 'Xqcicsr` (CSR)
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extension.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

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@@ -682,6 +682,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
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"CORE-V SIMD extensions custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32,
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"CORE-V Immediate Branching custom opcode table");
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TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32,
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"Qualcomm uC CSR custom opcode table");
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TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
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return MCDisassembler::Fail;

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

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AssemblerPredicate<(all_of FeatureVendorXwchc),
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"'Xwchc' (WCH/QingKe additional compressed opcodes)">;
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// Qualcomm Extension(s)
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def FeatureVendorXqcicsr
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: RISCVExperimentalExtension<"xqcicsr", 0, 2,
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"'Xqcicsr' (Qualcomm uC CSR Extension)">;
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def HasVendorXqcicsr
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: Predicate<"Subtarget->hasVendorXqcicsr()">,
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AssemblerPredicate<(all_of FeatureVendorXqcicsr),
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"'Xqcicsr' (Qualcomm uC CSR Extension)">;
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//===----------------------------------------------------------------------===//
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// LLVM specific features and extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td‎

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@@ -2064,6 +2064,7 @@ include "RISCVInstrInfoXSf.td"
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include "RISCVInstrInfoSFB.td"
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include "RISCVInstrInfoXCV.td"
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include "RISCVInstrInfoXwch.td"
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include "RISCVInstrInfoXqci.td"
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//===----------------------------------------------------------------------===//
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// Global ISel

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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//===---------------- RISCVInstrInfoXQci.td ----------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the vendor extensions defined by QUALCOMM.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Formats
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr" in {
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let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
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def QC_CSRRWR : RVInstR<0b1000110, 0b000, OPC_SYSTEM, (outs GPR:$rd),
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(ins GPR:$rs1, GPRNoX0:$rs2), "qc.csrrwr",
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"$rd, $rs1, $rs2">;
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def QC_CSRRWRI : RVInstR<0b1000111, 0b000, OPC_SYSTEM, (outs GPR:$rd),
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(ins uimm5:$rs1, GPRNoX0:$rs2), "qc.csrrwri",
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"$rd, $rs1, $rs2">;
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} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
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} // Predicates = [HasVendorXqcicsr, IsRV32], DecoderNamespace = "Xqcicsr"

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

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return getIncompatibleError("xwchc", "zcb");
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}
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if (Exts.count("xqcicsr") != 0 && (XLen != 32)) {
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return getError("'xqcicsr' is only supported for 'rv32'");
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}
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return Error::success();
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}
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‎llvm/test/CodeGen/RISCV/attributes.ll‎

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; RUN: llc -mtriple=riscv32 -mattr=+xtheadmempair %s -o - | FileCheck --check-prefix=RV32XTHEADMEMPAIR %s
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; RUN: llc -mtriple=riscv32 -mattr=+xtheadsync %s -o - | FileCheck --check-prefix=RV32XTHEADSYNC %s
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; RUN: llc -mtriple=riscv32 -mattr=+xwchc %s -o - | FileCheck --check-prefix=RV32XWCHC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s
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; RUN: llc -mtriple=riscv32 -mattr=+zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s
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; RUN: llc -mtriple=riscv32 -mattr=+zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
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; RUN: llc -mtriple=riscv32 -mattr=+zca %s -o - | FileCheck --check-prefixes=CHECK,RV32ZCA %s
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; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0"
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; RV32XTHEADSYNC: .attribute 5, "rv32i2p1_xtheadsync1p0"
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; RV32XWCHC: .attribute 5, "rv32i2p1_xwchc2p2"
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; RV32XQCICSR: .attribute 5, "rv32i2p1_xqcicsr0p2"
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; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo1p0"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc1p0"
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; RV32ZCA: .attribute 5, "rv32i2p1_zca1p0"

‎llvm/test/MC/RISCV/xqcicsr-invalid.s‎

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# Xqcicsr - Qualcomm uC CSR Extension
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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s
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# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \
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# RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s
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# CHECK: :[[@LINE+1]]:20: error: invalid operand for instruction
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qc.csrrwr x10, x5, x0
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.csrrwr x10, x5
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
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qc.csrrwr x10, x5, x20
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# CHECK: :[[@LINE+1]]:21: error: invalid operand for instruction
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qc.csrrwri x20, 31, x0
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# CHECK-PLUS: :[[@LINE+1]]:17: error: immediate must be an integer in the range [0, 31]
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qc.csrrwri x20, 45, x12
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# CHECK: :[[@LINE+1]]:1: error: too few operands for instruction
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qc.csrrwri x20, 23
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# CHECK-MINUS: :[[@LINE+1]]:1: error: instruction requires the following: 'Xqcicsr' (Qualcomm uC CSR Extension)
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qc.csrrwri x30, 31, x12

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