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[RISCV] Remove the declarations for xandesvpackfph LLVM IR intrinsics. NFC.
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‎llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadb.ll

Lines changed: 0 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,6 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvpackfph \
55
; RUN: -verify-machineinstrs -target-abi=lp64f | FileCheck %s
66

7-
declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.nxv1f16.f32(
8-
<vscale x 1 x half>,
9-
<vscale x 1 x half>,
10-
float,
11-
iXLen, iXLen);
12-
137
define <vscale x 1 x half> @intrinsic_vfpmadb_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, float %1, iXLen %2) nounwind {
148
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv1f16_nxv1f16_f32:
159
; CHECK: # %bb.0: # %entry
@@ -27,13 +21,6 @@ entry:
2721
ret <vscale x 1 x half> %a
2822
}
2923

30-
declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadb.mask.nxv1f16.f32(
31-
<vscale x 1 x half>,
32-
<vscale x 1 x half>,
33-
float,
34-
<vscale x 1 x i1>,
35-
iXLen, iXLen, iXLen);
36-
3724
define <vscale x 1 x half> @intrinsic_vfpmadb_mask_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
3825
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv1f16_nxv1f16_f32:
3926
; CHECK: # %bb.0: # %entry
@@ -53,12 +40,6 @@ entry:
5340
ret <vscale x 1 x half> %a
5441
}
5542

56-
declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.nxv2f16.f32(
57-
<vscale x 2 x half>,
58-
<vscale x 2 x half>,
59-
float,
60-
iXLen, iXLen);
61-
6243
define <vscale x 2 x half> @intrinsic_vfpmadb_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, float %1, iXLen %2) nounwind {
6344
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv2f16_nxv2f16_f32:
6445
; CHECK: # %bb.0: # %entry
@@ -76,13 +57,6 @@ entry:
7657
ret <vscale x 2 x half> %a
7758
}
7859

79-
declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadb.mask.nxv2f16.f32(
80-
<vscale x 2 x half>,
81-
<vscale x 2 x half>,
82-
float,
83-
<vscale x 2 x i1>,
84-
iXLen, iXLen, iXLen);
85-
8660
define <vscale x 2 x half> @intrinsic_vfpmadb_mask_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
8761
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv2f16_nxv2f16_f32:
8862
; CHECK: # %bb.0: # %entry
@@ -102,12 +76,6 @@ entry:
10276
ret <vscale x 2 x half> %a
10377
}
10478

105-
declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.nxv4f16.f32(
106-
<vscale x 4 x half>,
107-
<vscale x 4 x half>,
108-
float,
109-
iXLen, iXLen);
110-
11179
define <vscale x 4 x half> @intrinsic_vfpmadb_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, float %1, iXLen %2) nounwind {
11280
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv4f16_nxv4f16_f32:
11381
; CHECK: # %bb.0: # %entry
@@ -125,13 +93,6 @@ entry:
12593
ret <vscale x 4 x half> %a
12694
}
12795

128-
declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadb.mask.nxv4f16.f32(
129-
<vscale x 4 x half>,
130-
<vscale x 4 x half>,
131-
float,
132-
<vscale x 4 x i1>,
133-
iXLen, iXLen, iXLen);
134-
13596
define <vscale x 4 x half> @intrinsic_vfpmadb_mask_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
13697
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv4f16_nxv4f16_f32:
13798
; CHECK: # %bb.0: # %entry
@@ -151,12 +112,6 @@ entry:
151112
ret <vscale x 4 x half> %a
152113
}
153114

154-
declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.nxv8f16.f32(
155-
<vscale x 8 x half>,
156-
<vscale x 8 x half>,
157-
float,
158-
iXLen, iXLen);
159-
160115
define <vscale x 8 x half> @intrinsic_vfpmadb_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, float %1, iXLen %2) nounwind {
161116
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv8f16_nxv8f16_f32:
162117
; CHECK: # %bb.0: # %entry
@@ -174,13 +129,6 @@ entry:
174129
ret <vscale x 8 x half> %a
175130
}
176131

177-
declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadb.mask.nxv8f16.f32(
178-
<vscale x 8 x half>,
179-
<vscale x 8 x half>,
180-
float,
181-
<vscale x 8 x i1>,
182-
iXLen, iXLen, iXLen);
183-
184132
define <vscale x 8 x half> @intrinsic_vfpmadb_mask_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
185133
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv8f16_nxv8f16_f32:
186134
; CHECK: # %bb.0: # %entry
@@ -200,12 +148,6 @@ entry:
200148
ret <vscale x 8 x half> %a
201149
}
202150

203-
declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.nxv16f16.f32(
204-
<vscale x 16 x half>,
205-
<vscale x 16 x half>,
206-
float,
207-
iXLen, iXLen);
208-
209151
define <vscale x 16 x half> @intrinsic_vfpmadb_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, float %1, iXLen %2) nounwind {
210152
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv16f16_nxv16f16_f32:
211153
; CHECK: # %bb.0: # %entry
@@ -223,13 +165,6 @@ entry:
223165
ret <vscale x 16 x half> %a
224166
}
225167

226-
declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadb.mask.nxv16f16.f32(
227-
<vscale x 16 x half>,
228-
<vscale x 16 x half>,
229-
float,
230-
<vscale x 16 x i1>,
231-
iXLen, iXLen, iXLen);
232-
233168
define <vscale x 16 x half> @intrinsic_vfpmadb_mask_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
234169
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv16f16_nxv16f16_f32:
235170
; CHECK: # %bb.0: # %entry
@@ -249,12 +184,6 @@ entry:
249184
ret <vscale x 16 x half> %a
250185
}
251186

252-
declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.nxv32f16.f32(
253-
<vscale x 32 x half>,
254-
<vscale x 32 x half>,
255-
float,
256-
iXLen, iXLen);
257-
258187
define <vscale x 32 x half> @intrinsic_vfpmadb_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, float %1, iXLen %2) nounwind {
259188
; CHECK-LABEL: intrinsic_vfpmadb_vf_nxv32f16_nxv32f16_f32:
260189
; CHECK: # %bb.0: # %entry
@@ -272,13 +201,6 @@ entry:
272201
ret <vscale x 32 x half> %a
273202
}
274203

275-
declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadb.mask.nxv32f16.f32(
276-
<vscale x 32 x half>,
277-
<vscale x 32 x half>,
278-
float,
279-
<vscale x 32 x i1>,
280-
iXLen, iXLen, iXLen);
281-
282204
define <vscale x 32 x half> @intrinsic_vfpmadb_mask_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
283205
; CHECK-LABEL: intrinsic_vfpmadb_mask_vf_nxv32f16_nxv32f16_f32:
284206
; CHECK: # %bb.0: # %entry

‎llvm/test/CodeGen/RISCV/rvv/xandesvpackfph-vfpmadt.ll

Lines changed: 0 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -4,12 +4,6 @@
44
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zve64x,+xandesvpackfph \
55
; RUN: -verify-machineinstrs -target-abi=lp64f | FileCheck %s
66

7-
declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.nxv1f16.f32(
8-
<vscale x 1 x half>,
9-
<vscale x 1 x half>,
10-
float,
11-
iXLen, iXLen);
12-
137
define <vscale x 1 x half> @intrinsic_vfpmadt_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, float %1, iXLen %2) nounwind {
148
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv1f16_nxv1f16_f32:
159
; CHECK: # %bb.0: # %entry
@@ -27,13 +21,6 @@ entry:
2721
ret <vscale x 1 x half> %a
2822
}
2923

30-
declare <vscale x 1 x half> @llvm.riscv.nds.vfpmadt.mask.nxv1f16.f32(
31-
<vscale x 1 x half>,
32-
<vscale x 1 x half>,
33-
float,
34-
<vscale x 1 x i1>,
35-
iXLen, iXLen, iXLen);
36-
3724
define <vscale x 1 x half> @intrinsic_vfpmadt_mask_vf_nxv1f16_nxv1f16_f32(<vscale x 1 x half> %0, <vscale x 1 x half> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
3825
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv1f16_nxv1f16_f32:
3926
; CHECK: # %bb.0: # %entry
@@ -53,12 +40,6 @@ entry:
5340
ret <vscale x 1 x half> %a
5441
}
5542

56-
declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.nxv2f16.f32(
57-
<vscale x 2 x half>,
58-
<vscale x 2 x half>,
59-
float,
60-
iXLen, iXLen);
61-
6243
define <vscale x 2 x half> @intrinsic_vfpmadt_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, float %1, iXLen %2) nounwind {
6344
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv2f16_nxv2f16_f32:
6445
; CHECK: # %bb.0: # %entry
@@ -76,13 +57,6 @@ entry:
7657
ret <vscale x 2 x half> %a
7758
}
7859

79-
declare <vscale x 2 x half> @llvm.riscv.nds.vfpmadt.mask.nxv2f16.f32(
80-
<vscale x 2 x half>,
81-
<vscale x 2 x half>,
82-
float,
83-
<vscale x 2 x i1>,
84-
iXLen, iXLen, iXLen);
85-
8660
define <vscale x 2 x half> @intrinsic_vfpmadt_mask_vf_nxv2f16_nxv2f16_f32(<vscale x 2 x half> %0, <vscale x 2 x half> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
8761
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv2f16_nxv2f16_f32:
8862
; CHECK: # %bb.0: # %entry
@@ -102,12 +76,6 @@ entry:
10276
ret <vscale x 2 x half> %a
10377
}
10478

105-
declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.nxv4f16.f32(
106-
<vscale x 4 x half>,
107-
<vscale x 4 x half>,
108-
float,
109-
iXLen, iXLen);
110-
11179
define <vscale x 4 x half> @intrinsic_vfpmadt_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, float %1, iXLen %2) nounwind {
11280
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv4f16_nxv4f16_f32:
11381
; CHECK: # %bb.0: # %entry
@@ -125,13 +93,6 @@ entry:
12593
ret <vscale x 4 x half> %a
12694
}
12795

128-
declare <vscale x 4 x half> @llvm.riscv.nds.vfpmadt.mask.nxv4f16.f32(
129-
<vscale x 4 x half>,
130-
<vscale x 4 x half>,
131-
float,
132-
<vscale x 4 x i1>,
133-
iXLen, iXLen, iXLen);
134-
13596
define <vscale x 4 x half> @intrinsic_vfpmadt_mask_vf_nxv4f16_nxv4f16_f32(<vscale x 4 x half> %0, <vscale x 4 x half> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
13697
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv4f16_nxv4f16_f32:
13798
; CHECK: # %bb.0: # %entry
@@ -151,12 +112,6 @@ entry:
151112
ret <vscale x 4 x half> %a
152113
}
153114

154-
declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.nxv8f16.f32(
155-
<vscale x 8 x half>,
156-
<vscale x 8 x half>,
157-
float,
158-
iXLen, iXLen);
159-
160115
define <vscale x 8 x half> @intrinsic_vfpmadt_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, float %1, iXLen %2) nounwind {
161116
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv8f16_nxv8f16_f32:
162117
; CHECK: # %bb.0: # %entry
@@ -174,13 +129,6 @@ entry:
174129
ret <vscale x 8 x half> %a
175130
}
176131

177-
declare <vscale x 8 x half> @llvm.riscv.nds.vfpmadt.mask.nxv8f16.f32(
178-
<vscale x 8 x half>,
179-
<vscale x 8 x half>,
180-
float,
181-
<vscale x 8 x i1>,
182-
iXLen, iXLen, iXLen);
183-
184132
define <vscale x 8 x half> @intrinsic_vfpmadt_mask_vf_nxv8f16_nxv8f16_f32(<vscale x 8 x half> %0, <vscale x 8 x half> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
185133
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv8f16_nxv8f16_f32:
186134
; CHECK: # %bb.0: # %entry
@@ -200,12 +148,6 @@ entry:
200148
ret <vscale x 8 x half> %a
201149
}
202150

203-
declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.nxv16f16.f32(
204-
<vscale x 16 x half>,
205-
<vscale x 16 x half>,
206-
float,
207-
iXLen, iXLen);
208-
209151
define <vscale x 16 x half> @intrinsic_vfpmadt_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, float %1, iXLen %2) nounwind {
210152
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv16f16_nxv16f16_f32:
211153
; CHECK: # %bb.0: # %entry
@@ -223,13 +165,6 @@ entry:
223165
ret <vscale x 16 x half> %a
224166
}
225167

226-
declare <vscale x 16 x half> @llvm.riscv.nds.vfpmadt.mask.nxv16f16.f32(
227-
<vscale x 16 x half>,
228-
<vscale x 16 x half>,
229-
float,
230-
<vscale x 16 x i1>,
231-
iXLen, iXLen, iXLen);
232-
233168
define <vscale x 16 x half> @intrinsic_vfpmadt_mask_vf_nxv16f16_nxv16f16_f32(<vscale x 16 x half> %0, <vscale x 16 x half> %1, float %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
234169
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv16f16_nxv16f16_f32:
235170
; CHECK: # %bb.0: # %entry
@@ -249,12 +184,6 @@ entry:
249184
ret <vscale x 16 x half> %a
250185
}
251186

252-
declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.nxv32f16.f32(
253-
<vscale x 32 x half>,
254-
<vscale x 32 x half>,
255-
float,
256-
iXLen, iXLen);
257-
258187
define <vscale x 32 x half> @intrinsic_vfpmadt_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, float %1, iXLen %2) nounwind {
259188
; CHECK-LABEL: intrinsic_vfpmadt_vf_nxv32f16_nxv32f16_f32:
260189
; CHECK: # %bb.0: # %entry
@@ -272,13 +201,6 @@ entry:
272201
ret <vscale x 32 x half> %a
273202
}
274203

275-
declare <vscale x 32 x half> @llvm.riscv.nds.vfpmadt.mask.nxv32f16.f32(
276-
<vscale x 32 x half>,
277-
<vscale x 32 x half>,
278-
float,
279-
<vscale x 32 x i1>,
280-
iXLen, iXLen, iXLen);
281-
282204
define <vscale x 32 x half> @intrinsic_vfpmadt_mask_vf_nxv32f16_nxv32f16_f32(<vscale x 32 x half> %0, <vscale x 32 x half> %1, float %2, <vscale x 32 x i1> %3, iXLen %4) nounwind {
283205
; CHECK-LABEL: intrinsic_vfpmadt_mask_vf_nxv32f16_nxv32f16_f32:
284206
; CHECK: # %bb.0: # %entry

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